- 您现在的位置：买卖IC网 > PDF目录69326 > S1S60000F00A100 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 PDF资料下载
参数资料
| 型号： | S1S60000F00A100 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP15-100 |
| 文件页数： | 15/83页 |
| 文件大小： | 1024K |
| 代理商： | S1S60000F00A100 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页
S1S60000 Technical Manual
16
EPSON
Rev.1.5
3.2
Management Interface
S1S60000 supports MII management interface.
It can write or read registers in PHY through this interface.
Fig.3.3 and 3.4 show the waveforms in the read and write operations, respectively.
Fig.3.3
MII Management Interface Read Operation
Fig.3.4
MII Management Interface Write Operation
3.3
Connecting PHY Chips
Fig.3.5 shows connection between S1S60000 and PHY chips.
You do not have to connect CRS for Full Duplex communication only.
Also, TX_ER signal is not connected.
[ Important ]
Make necessary setting so that the PHY chip address becomes 0
×01 all the time. Operation cannot be
guaranteed if set to any other setting.
In the normal operation and the power save mode, OSC pin on S1S60000 outputs the signal being formed after
buffering OSC3 input.
Thus connecting a 25MHz crystal oscillator to OSC3 input and connecting OSCO to the
clock of PHY allows you operate both S1S60000 and PHY with a single crystal oscillator.
Note: Before supplying clock form OSCO to PHY, make sure that it meets the clock accuracy required by PHY.
Also make sure that length of the pattern connected is minimized and the clock waveform satisfies
requirements of the PHY specification.
After deciding a PHY chip to be used, acquire result of auto negotiation, speed (100BASE/10BASE) established
by link and bit information showing the mode (Full Duplex/ Half Duplex) and arrange so that they are reflected
to the ANEGR register. (Realtek Company’s RTL8201L is not equipped with a register for storing result of auto
negotiation and cannot be used for S1S60000. )
Acquiring Method of ANEGR Register Value
(1) Seek for a register in which result of auto negotiation can be stored. In general, it is available between 16 and
19 or at 24 or 25.
(2) Set the value obtained by subtracting 16 from the register offset to LSOFF bit.
(3) Set DINV and SINV according to the result storing method.
(4) Set each bit of DUPLEX and SPEED depending on the result store bit position.
32bit
preamble Start of
frame
read
Z 1 1 1
1 0 1 1 0 A A A A A R R R R R Z 0 D D D D D
D Z
PHY
address
PHY
register
Turnaround
16bit
Data
MDC
MDIO
32bit
preamble Start of
frame
write
Z 1 1 1
1 0 1
1
0
A A A A A R R R R R 1 0 D D D D D
D Z
PHY
address
PHY
register
Turnaround
16bit
Data
MDC
MDIO
相关PDF资料 |
PDF描述 |
|---|---|
| S202T01 | TRIGGER OUTPUT SOLID STATE RELAY, 3000 V ISOLATION-MAX |
| S102T01 | TRIGGER OUTPUT SOLID STATE RELAY, 3000 V ISOLATION-MAX |
| S3C4510BXX-QE | 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP208 |
| S3C72E8XX-QX | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP100 |
| S3C72N4XX-QT | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S1S60000F00A300 | 制造商:Epson Electronics America Inc 功能描述:IC NETWORK CONTROLLER |
| S1S60000F00A30B | 制造商:Epson Electronics America Inc 功能描述:IC NETWORK CONTROLLER |
| S1S60000F00A500 | 制造商:Epson Electronics America Inc 功能描述:IC NETWORK CONTROLLER |
| S1S65000F00A100 | 功能描述:IC WEB CAMERA 128-QFP RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| S1S65010 | 制造商:EPSON 制造商全称:EPSON 功能描述:Network Camera Controller with JPEG Encoder |
发布紧急采购，3分钟左右您将得到回复。