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参数资料
| 型号： | S1S60000F00A100 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP15-100 |
| 文件页数： | 26/83页 |
| 文件大小： | 1024K |
| 代理商： | S1S60000F00A100 |
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S1S60000 Technical Manual
26
EPSON
Rev.1.5
4.4
Data Swap by Use of Endian
Data is processed in the form of Little Endian inside S1S60000.
On the other hand, for matching the
connection of Big Endian CPU, S1S60000 swaps data as needed by setting Endian and with the access port and
reduces data swapping load on the host CPU side. When an appropriate endian and bus size are selected, you
need not be conscious of the swap.
The following shows when data is swapped practically:
Following describes examples of actual swap procedures.
When accessing the command/status port
Swapping is carried out on the command/status port so that bit orders on the 16-bit register in the host CPU and
on the register in S1S60000 become the same. Specifically, the swap is carried out when the big endian and
8-bit bus width are selected.
When accessing the data port
When a continued byte string on the memory is transferred, swap on the data port ensures the same byte order
on the CPU and S1S60000.
Specifically, the swap becomes available when the big endian and 16-bit bus size
are selected.
Table 4.11 shows state of the data being written from the host CPU and obtained by S1S60000.
Table 4.12
shows state of data being written from S1S60000 and obtained by the host CPU.
Table 4.11
Data Obtained by S1S60000 in Write Operation
R/W
Endian
Bus
size
Operation
Command port
1234h write operation
Data port
5678h write operation
Word
1234
5678
LOW Byte
xx34
xx78
16bit
HIGH Byte
12xx
56xx
LOW Byte
xx34
xx78
Little
8bit
HIGH Byte
xx12
xx56
Word
1234
7856(*1)
LOW Byte
12xx
78xx(*1)
16bit
HIGH Byte
xx34
xx56(*1)
LOW Byte
xx12(*1)
xx78
Write
Big
8bit
HIGH Byte
xx34(*1)
xx56
xx: Uncertain
*1: The upper and lower bytes are transposed by the swap operation.
Table 4.12
Data Obtained by Host CPU in Read Operation
R/W
Endian
Bus
size
Operation
Status port
1234h read operation
Data port
5678h read operation
Word
1234
5678
LOW Byte
zz34
zz78
5678(*2)
16bit
HIGH Byte
12zz
56zz
5678(*2)
LOW Byte
zz34
zz78
Little
8bit
HIGH Byte
zz12
zz56
Word
1234
7856(*1)
LOW Byte
12zz
78zz(*1)
7856(*1, *2)
16bit
HIGH Byte
zz34
zz56(*1)
7856(*1, *2)
LOW Byte
zz12(*1)
zz78
Read
Big
8bit
HIGH Byte
zz34(*1)
zz56
zz: HIGH impedance, but forced to FFh by the pull-up register.
*1: The upper and lower bytes are transposed by the swap operation.
*2: As for Type0, 16-bit long data is output on the bus, but 8 the host CPU acquires bits alone.
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