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| 型号： | S1S60000F00A100 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP15-100 |
| 文件页数： | 27/83页 |
| 文件大小： | 1024K |
| 代理商： | S1S60000F00A100 |
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S1S60000 Technical Manual
Rev.1.5
EPSON
27
4.5
Access Timing
Writing from the host interface to S1S60000 takes place asynchronously and the state of the signals changes
independent of the internal bus clock of S1S60000.
Thus, S1S60000 samples state of the host interface signals
continuously with the internal bus clock and, after detecting the access state, implements the write operation
when it detects the non-access state first.
The bus cycle of the host CPU, therefore, must be set to allow at least
three times of sampling (2 cycles with the internal bus clock
+ more than the setup time). Since cycles of the
sampling timing can vary according to the internal bus clock, special attention is required when operating
S1S60000 at a low internal bus clock.
Table 4.13
Access Time required depending on Operation Mode
OSC3 input
Operation
mode
Internal bus
clock
Minimum access period
(ns)(*1)
25MHz
Normal
50MHz
45
25MHz
Power save
12.5MHz
165
20MHz
Normal
40MHz
55
10MHz
Normal
20MHz
105
*1: The period in which access with the host interface input signal is maintained
Fig.4.2 shows the sampling timing for the write.
Fig.4.2
Sampling Timing for Write
(1): The timing when the write condition is met for the first time.
The data is acquired and held temporarily.
(2): The timing when the write condition is met for the second time.
The data is acquired again, used to
overwrite (1) data and then held temporarily.
(3): The timing when non-access state is detected for the first time.
At the time, no data is acquired. Data
acquired by this timing is acquired inside S1S60000.
Operations at respective read timings are essentially the same as the write operation though the data bus drive
timing is not identical.
Fig.4.3 shows the sampling timing.
(1)
(2)
(3)
HCS#
Conditions for write
HDATA[15:0]
Write
Valid
Invalid
Internal bus clock
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