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参数资料
| 型号： | S1S60000F00A100 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP15-100 |
| 文件页数： | 3/83页 |
| 文件大小： | 1024K |
| 代理商： | S1S60000F00A100 |
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S1S60000 Technical Manual
Rev.1.5
EPSON
5
Pin name
Pin No.
I/O
Function
HMUX
84
I
Host Bus Multiplex
It sets whether the address bus and the data bus of the host interface
are multiplexed in time-sharing. In case of multiplex, a latched HD[2:0]
is used instead of HA[2:0]. The control line to be used for latching
varies with the CPU type selected with HIFSEL.
1:Separate bus, 0:Multiplex bus
This pin was not used in our specifications before Rev.1.3 and is set
as a separate bus type when nothing is connected to.
Connect this
pin to GND only when a multiplex bus is used.
State of this pin is acquired to the HIFCR register at reset.
This pin
contains the pull-up resistor.
HINTPOL
85
I
Host Interrupt Polarity Select:
It is the polarity select pin for HRQI and HDVI when they are active.
1:HIGH active, 0:LOW active
State of this pin is acquired to HIFCR at reset.
This pin contains the
pull-up resister.
HENDIAN
92
I
Host Interface Endian Select:
It is the endian type select pin. Appropriately selecting the type for a
CPU to be used allows switching the upper and lower data on the
command or status port and on the data port.
1:Big Endian, 0:Little Endian
State of this pin is acquired to the HIFCR register at reset.
This pin
contains the pull-up resistor.
HSIZE
93
I
Host Bus Size Select:
It is the interface size select pin.
It is used to specify the data bus
size when accessing the port.
1:8bit, 0:16bit
State of this pin is acquired to HIFCR at reset.
This pin contains the
pull-up resister.
1.4.2.3
MII Interface Signals
Table 1.3
List of MII Interface Signals
Pin name
Pin No.
I/O
Function
MII_RXCLK
35
I
MII Receive Clock:
Receiving clock entered from PHY chip.
It is the reference clock of
MII_RXD [3:0], MII_RXDV.
Its frequency is 2.5MHz for 10BASE-T
and 25MHz for 100BASE-TX.
MII_RXD[3:0]
40 to 37
I
MII Receive Data:
Receive data entered from PHY chip.
MII_RXDV
36
I
MII Receive Data Valid:
Input signal from PHY chip.
If it is HIGH at the positive going edge
of MII_RXCLK, MII_RXD [3:0] is valid.
MII_TXCLK
33
I
MII Transmit Clock:
Transmit clock entered from PHY chip.
It is the reference clock of
MII_TXD [3:0], MII_TXEN.
Its frequency is 2.5MHz for 10BASE-T
and 25MHz for 100BASE-TX.
MII_TXD[3:0]
27 to 30
O
MII Transmit Data:
Transmit data output to PHY chip.
MII_TXEN
31
O
MII Transmit Enable:
Output signal to PHY chip.
If it is HIGH at the positive going edge of
MII_TXCLK, MII_TXD[3:0] is valid.
MII_RXER
34
I
MII Receive Error:
Input signal from PHY chip.
This signal indicates that receive data
contained an error.
It is valid on 100BASE-TX alone and ignored on
10BASE-T.
MII_COL
26
I
MII Collision Detect:
It indicates that collision of signals occurred during Half Duplex
communication.
MDC
41
O
MII Management Interface Clock:
It is the clock used to set up function of PHY chip as well as control it
and read its status.
This signal is output from S1S60000.
MDIO
pin sends or receives data in synchronization with this signal.
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