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| 型号： | S1S60000F00A100 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP15-100 |
| 文件页数： | 18/83页 |
| 文件大小： | 1024K |
| 代理商： | S1S60000F00A100 |
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S1S60000 Technical Manual
Rev.1.5
EPSON
19
4.2
Host Interface Port
4.2.1
Command Port
This port is used to send a command from the host CPU to S1S60000.
Since this port is 16-bit wide, two times
of access (the upper and lower addresses) are required when the 8-bit interface is used.
For detail of the
commands, refer to the “SIS60000 Series Host I/F Manual”.
4.2.2
Status Port
This port is used to return a status from S1S60000 to the host CPU.
Since this port is 16-bit wide, two times of
access (the upper and lower addresses) are required when the 8-bit interface is used.
For detail, refer to the
“SIS60000 Series Host I/F Manual”.
4.2.3
Data Port
This port is used to transmit and receive data between the host CPU and S1S60000.
Since this port is 16-bit
wide, two accesses to the upper address and to the lower address are required when an 8-bit interface is used.
Option segments added to a command or status are also transmitted and received through this port. For the detail
of options, refer to the “SIS60000 Series Host I/F Manual.”
Data are written from the host CPU to the data port only after the WRITE status is returned to the SEND
command. At the time, be sure to check the states of HSTREN (bit4) and H2CDV/H2CDC (bit3) of the flag port
after each writing before another writing.
4.2.4
Flag Port
This port is used to indicate how a host interface-related command, status or data is processed.
One of the
following two types is assigned according to setting of EXTINT (bit7).
When EXTINT = 0, the state of bit [1:0] is the factor that activates the HINT signal, and when any of the bits is 1,
the HINT signal goes active (polarity of the signal is changeable). Reading status or data on the host side clears
corresponding factors, and when all factors are cleared, the HINT signal turns to inactive.
Also, the data
processing state inside S1S60000 is checked from the host side according to the state of bit[3:2].
When EXTINT = 1, the state of bit [3:0] is the factor that activates the HINT signal, and when any of the bits is 1,
the HINT signal goes active (polarity of the signal is changeable). Bit3 and 2 can be cleared by writing 1 at the
corresponding bit position on the host side, and when all factors are cleared, the HINT signal turns to inactive.
This port is 8-bit wide.
Thus, when the 16-bit interface is used or when two times of access (to the upper and
lower addresses) are made from the 8-bit interface, the same data is read to the upper and lower bits.
Table 4.2
Flag Port Bit Assignment
bit
EXTINT=0
EXTINT=1
7
EXTINT
Extended interrupt use changeover (R/W)
0: Extended interrupt is not used. (So far compatible)
1: Extended interrupt is used.
6:5
Not used.
Value is 0.
4
HSTREN
State of data port receiving circuit (R/O)
0: Data port receiving circuit is disabled.
1: Data port receiving circuit is enabled.
3
H2CDV
Write data processing state
(R/O)
0: Data write available
1: Waiting for data read
H2CDC
Data read complete notice (Read)
0: Waiting for data read or data is absent
1: Read of preceding data is complete
(it is cleared as 1 is written)
2
H2CCV
Command processing state
(R/O)
0: Command write is available.
1: Waiting processing of command.
H2CCC
Command processing complete notice
(Read)
0: Command is not processed yet or command is not
present.
1: Processing of preceding command is complete.
(It is cleared as 1 is written.)
1
C2HDV
Read data preparation state (R/O)
0: Data to be read is not present.
1: Data to be read is present. (It is cleared as data is read.)
0
C2HSV
Status preparation state (R/O)
0: Status to be read is not present.
1: Status to be read is present. (It is cleared as status is read.)
Note:
When the host interface is 16 bits wide, the same information is output to bit [15:8] and bit [7:0].
Writing is enabled to bit [7:0] alone.
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