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| 型号： | S1S60000F00A100 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP15-100 |
| 文件页数： | 19/83页 |
| 文件大小： | 1024K |
| 代理商： | S1S60000F00A100 |
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S1S60000 Technical Manual
20
EPSON
Rev.1.5
4.3
Host Interface Type
The host interface type is selected at hardware reset according to the HIFSEL[2:0] pin status as well as the
HIFCR data in the EEPROM.
Table 4.3 shows assignment of the host interface type.
Table 4.3
Host Interface Type
HIFSEL[2:0]
Type
Example of host CPUs (8/16bit bus)
000
Type 0
Hitachi SH-3/4, EPSON S1C33
001
Type 1
MC68000/10
010
Type 2
MC68030/40
011
Type 3
Generic
100
Type 4
Reserved
101
Type 5
MIPS, ISA, NEC VR4121(16bit)
110
Type 6
PCMCIA, Philips PR31500/PR31700, Toshiba TX3912
111
EEPROM
A type is selected in the range of Type0 to Type6 depending on HIFCR
data of EEPROM
Type0
This type of interface controls access by use of the independent write signals (byte basis)
and a single read signal.
Hitachi SH-3/4 and EPSON S1C33 belong to this type.
Type1
It controls access by combining the upper/lower byte signal (such as UDS#/LDS#) and the
read/write signal.
Motorola’s MC68000 belongs to this type.
In this case, connect the
upper byte select signal to HWR0#, the lower byte select signal to HWR1# and the
read/write signal to HRD1#.
And maintain RD0# unconnected.
Type2
It controls access by combining the data transfer size indicate signal and the read/write
signal.
MC68030/40 belong to this type.
In this case, connect SIZ0 signal to HWR0#,
SIZ1 signal to HRD0# and the read/write signal to HRD1#.
And maintain HWR1#
unconnected.
Type3
It is the general-purpose type.
When a given host CPU does not fit into any type, it is
used to connect such host CPU by use of an externally generated access signal.
In this
case, connect the lower byte write signal to HWR0#, the upper byte write signal to HWR1#,
the lower byte read signal to HRD0# and the upper byte read signal to HRD1#.
Type4
This type is reserved for future extension.
Don’t select it.
Type5
It controls access by using the upper/lower byte select signal (composed of two or more
signals) plus the independent read signal and the write signals.
MIPS and ISA bus belong
to this type.
In this case, connect the write signal to HWR0#, the upper byte select signal
to HWR1# and the read signal to HRD0#.
Maintain RD1# unconnected.
Type6
It controls access by use of the independent byte enable signal, independent read enable
signal and write signal.
PCMCIA interface belongs to this type.
In this case, connect
the write signal to HWR0#, the read signal to HRD0# and the lower byte enable signal to
HRD1#.
EEPROM
It selects a type according to HIFCR data of the serial EEPROM.
A type is selectable in
the range of Type0 to Type6.
When EEPROM data is “111” or when EEPROM is not
connected, S1S60000 assumes that a host CPU is unconnected.
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