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参数资料
| 型号： | S1S60000F00A100 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP15-100 |
| 文件页数： | 20/83页 |
| 文件大小： | 1024K |
| 代理商： | S1S60000F00A100 |
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S1S60000 Technical Manual
Rev.1.5
EPSON
21
Multiplex Bus
Some CPUs use parts or the whole of address lines commonly with data bus in time sharing. Before such CPUs
are connected to S1S60000, it is necessary to make HMUX “0” and to implement multiplex setting. After the
setting, a signal that latched HD[2:0] is used as the address instead of HA[2:0]. For the latch signal, use a signal
that becomes HIGH during address output period and that turns to LOW while the address is settled, and input it
to the following signal lines for each type:
Type0=HRD1#, Type1=HRD0#, Type2=HWR1#, Type5=HRD1#
However, multiplex bus cannot be set for Type 3 (Generic) and Type 6 (PCMCIA).
Fig.4.1 shows the CPU type selection flowchart.
Identify type of the target CPU based on its signal line and
then check whether an appropriate access is obtainable or not referencing the signal pattern of respective CPUs in
Tables 4.5 to 4.10.
If the selected pattern does not match the signal pattern, decode the signal externally so that
it matches the CPU type of Type 3 Generic or similar pattern.
Fig.4.1
Host Interface Type Selection Flowchart
Are Read signal
and Write signal
separated?
START
Is Write for upper
er byte
independent
?
Check referencing
Type0
Is it ISA type?
Y
N
Y
N
Check referencing
Type5
Y
Is it
PCMCIA
type?
N
Check referencing
Type6
Y
Is upper/lower byte
select signal
available?
Check referencing
Type1
Y
N
Check referencing
Type2
N
Connect to Type3
/lower byte
independent?
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| S1S60000F00A300 | 制造商:Epson Electronics America Inc 功能描述:IC NETWORK CONTROLLER |
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| S1S65000F00A100 | 功能描述:IC WEB CAMERA 128-QFP RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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