
S1S60000 Technical Manual
Rev.1.5
EPSON
37
5.2.3
GENCR
(General Configuration Register: offset 4h)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
DISBC
DDSTEN
Reserved
SLPEN
PSEN
SERCONF[2:0]
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ESKDIV[1:0]
MDCDIV[1:0]
Reserved
bit
Name
Init.
Description
15
DISBC
0
(Disable Broadcast Receive)
Used to specify whether broadcast packets are to be received or not.
This
function is used only under limited conditions.
It should normally be set to 0.
0: Receives broadcast packets
1: Does not receive broadcast packets
14
DDSTEN
0
(Default Destination Massaging enable)
When the INT0 function (separate GPIO0 function) is enabled, the interrupt
notice function is enabled and DDSTEN indicates that the destination address
of the notice transmission is enabled.
0: Interrupt notice function is invalid
1: Interrupt notice function is valid and DADR0H, DADR0L is valid
13
Reserved
0
Reserved.
Be sure to set 0.
12
SLPEN
0
(Sleep Mode Enable)
Selects use or non-use of the sleep mode as the power management.
For
the sleep mode, refer to Chapter 6.
0: Does not use the sleep mode
1: Use the sleep mode
When PMWAIT = 0, however, the sleep mode is not available despite of the
setting of this bit.
11
PSEN
0
(Power Save Mode Enable)
It reduces the operating clock to 1/4 of the normal level in order to save power
consumption.
0: Does not use the power save mode.
1: Use the power save mode.
10:8
SERCONF
000
(Serial Configuration)
When the serial Interface pin (alternate function of GPIO[15:8] is enabled, it
specifies how to use the pin.
000: Hardware control mode (Note 1)
010: Serial emulation mode Active Open (Client operation)
011: Serial emulation mode Passive Open (Server operation)
Other than the above:
Reserved.
Note 1 : A fixed operation all the time irrespective of state of the
GPIO10/MODE pin.
7:6
ESKDIV
00
(EEPROM Serial Clock Divide)
It is used specify how the EEPROM Interface clock should be divided in
comparison with the internal bus clock.
The slower the clock is, the longer
becomes the time required for the access.
Set an appropriate time on the
EEPROM connected.
11:/32
10:/64
01:/128
00:/256
5:4
MDCDIV
00
(MIF Clock Divide)
It is used to specify how the MII Management Interface clock should be divided
in comparison with the internal bus clock.
The slower the clock is, the longer
becomes the time required for the access.
Set an appropriate division so that
the clock may be 4MHz maximum.
11:1/4
10:1/8
01:1/16
00:1/32
3:0
Reserved
0000 Reserved.
Be sure to set 0.