参数资料
型号: S1S60000F00A100
元件分类: 微控制器/微处理器
英文描述: 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封装: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP15-100
文件页数: 62/83页
文件大小: 1024K
代理商: S1S60000F00A100
S1S60000 Technical Manual
Rev.1.5
EPSON
59
6.
POWER MANAGEMENT CONTROL
The power save mode and the sleep mode are available on S1S60000 as the power management mode.
When
turning on these modes, enable the corresponding bit of GENCR register and then, in case of the sleep mode,
specify the timer value.
Normal mode
It is the mode used for normal operation.
The internal bus clock (=CPU clock) becomes twice the OSC3 clock.
Power save mode
In this mode, the internal bus clock operates at 1/4 of the normal setting (1/2 of OSC3 clock) to reduce power
consumption of S1S60000.
You can enable this mode by setting “1” on bit 11 (PSEN) of GENCR register.
Since the internal bus clock is modified, you must pay attention the related timing.
If a necessary timing is not
met, you must modify the setting.
(1) Setting of GENCR register ESKDIV (EEPROM Interface clock)
(2) Setting of GENCR register MDCDIV (MII management Interface clock)
(3) Setting of I2CCONF register SCLCNT (I2C master clock)
(4) Host Interface sampling interval
Note:
As long as this mode is enabled, 100BASE-TX based communication is unavailable.
To change the ESKDIV settings, use a method that will not change the EEPROM initial values.
After
the EEPROM is reset, Auto Load sets the GENCR register and, until the system enters the power save
mode, it operates with the clock that results from dividing the Normal mode clock with ESKDIV.
During this time, the EP_SK clock may exceed the allowable input frequency of connected elements.
Sleep mode
In this mode, core CPU operates on 32kHz of OSC1 and OSC3 circuit is stopped.
Power consumption of
S1S60000 is reduced to approximately 1/30 of the normal operation.
You can stop external OSC by setting
GPALT7 bit of GPALT register to “1” and connecting GPIO7 pin to the oscillation control pin (Active LOW) of
external OSC.
This arrangement further reduces the power consumption.
When enabling this mode, set SLPEN of GENCR register to “1” and then set the timer value (until this mode is
turned on from the power down mode) on SLPWAIT (bit[11:8]) of PMWAIT register.
Note: Be sure to feed power while the sleep mode is turned on.
If the operating supply voltage is not
maintained, results of the succeeding operations become unpredictable.
The sleep mode is turned on in the following procedure.
(1) S1S60000 sends the sleep status notice to the host CPU
(2) Specifies GPIO0 as the recovery trigger input in order to prohibit interrupt from other
(3) Switching the Operation Clock to OSC1
(4) When GPIO7 is specified as OSCCTL, selects OSCCTL=“0” in order to stop the external oscillator.
(5) Executes slp
Recovery starts when the LOW level is entered to GPIO0 and proceeds according to the following procedures:
(1) When GPIO7 is specified as OSCCTL, S1S60000 starts the external oscillator
(2) Starts up OSC3 oscillation circuit and waits until oscillation is stabilized
(3) Switching the Operation Clock to OSC3
(4) Sends the wake up status notice to the host CPU after recovery
Fig.6.1
Power Management Status Transition
Sleep mode
SLPEN=“1” & SLPWAIT Timeup
GPIO0=“0” Level
Normal operation mode
(Power save mode
when PSEN=“1”)
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