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| 型号： | S1S60000F00A100 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP15-100 |
| 文件页数： | 5/83页 |
| 文件大小： | 1024K |
| 代理商： | S1S60000F00A100 |
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S1S60000 Technical Manual
Rev.1.5
EPSON
7
1.4.2.5
General Purpose Input and Output Pins
Table 1.5
List of General Purpose Input and Output Pins
Pin name
Pin No.
I/O
Function
GPIO0/INT0
17
I/O
GPIO1
16
I/O
GPIO2/CRS
15
I/O
GPIO3
14
I/O
GPIO4
13
I/O
GPIO5
12
I/O
GPIO6
11
I/O
GPIO7/OSCCTL
10
I/O
General Purpose I/O [7:0]:
They are general purpose input/output pins. They accept 5V
input.
GPIO0 is used as an interrupt pin and allows sending interrupt
notice to a previously specified destination. GPIO2 is used as the
CRS input pin in Half Duplex communication. GPIO7 can be
used as the OSC control pin in the sleep mode. For the detail,
refer to Chapter 5.3.
After the hardware is reset, all pins are used for input only.
GPIO8/RXD
8
I/O
GPIO9/TXD
7
I/O
GPIO10/MODE
6
I/O
GPIO11/RSV1
5
I/O
GPIO12/CTS#
4
I/O
GPIO13/DSR#
3
I/O
GPIO14/RTS#
2
I/O
GPIO15/DTR#
1
I/O
General Purpose I/O [15:8]:
General-purpose input/output pin for 3.3V CMOS level and
Schimitt input.
They can be used as start-stop synchronous
serial terminals by setting GPLLT register.
For details, refer to
Chapter 2.3.
After the hardware reset, all pins are used for input only.
1.4.2.6
Clock Generator Pins
Table 1.6
List of Clock Generator Pins
Pin name
Pin No.
I/O
Function
OSC1
46
I
OSC2
43
O
OSC1 clock pin
When using the sleep mode in the power management, it is used to
connect 32.768kHz crystal.
S1S60000 in the sleep mode is
operated with this clock.
When the sleep mode is not used,
connect OSC1 to VSS and open OSC2.
OSC3
89
I
OSC4
87
O
OSC3 clock pin (for oscillation of crystal/ceramics or for input of
external clock)
Operating clock oscillation pin for S1S60000. A crystal transducer of
10 to 25MHz is connected. When entering an external clock, input a
clock of 10 to 25MHz to OSC3 and make OSC4 open.
It is advised to use a clock of 25MHz normally. When any other
frequency is used, communication with 100BASE-TX and the
power save mode may become unavailable.
OSCO
94
O
OSC output pin
It is used to generate buffered output of OSC3 input.
Frequency of
output from this pin is the same as that OSC3 input.
Supplying
clock to PHY chip from this pin helps reducing number of oscillators
for PHY.
Note: When supplying clock from this pin, be sure to use a crystal
oscillator that can meet the frequency accuracy required by PHY
chip.
Normally, 50ppm maximum accuracy is required.
PLLC
80
-
PLL capacitor connecting pin
It is the capacitor connecting pin for doubling OSC3 frequency with
the internal PLL. Be sure to connect R and C shown in Fig.1.3.
Unless they are connected, this IC does not operate normally.
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