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| 型号： | S1S60000F00A100 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP15-100 |
| 文件页数： | 17/83页 |
| 文件大小： | 1024K |
| 代理商： | S1S60000F00A100 |
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S1S60000 Technical Manual
18
EPSON
Rev.1.5
4.
HOST INTERFACE
The host interface is for connecting S1S60000 to external CPU and is of 8-bit or 16-bit parallel type. The host
interface allows connecting six types of CPUs directly depending on its setting.
4.1
Control Signals
Table 4.1 shows the host interface signals.
Every input pin including I/O pins contain a pull-up resister
enabling then to accept 5V input is acceptable for HCS#, HA [2:0], HD [15:0], HRD0#, HRD1#, HWR0# and
HWR1#.
Output is 3.3V CMOS or 3-state output.
When not using the host interface (when implementing
GPIO control independently, for instance), be sure to leave the every host interface signal unconnected.
Table 4.1
Host Interface Signals
Pin name
I/O
Function
HCS#
I
It is the access enable signal.
Access available as it goes LOW.
HA[2:0]
I
Port select signal
HD[15:0]
I/O
Input/output data bus
HRD0#
I
A R/W control signal.
Its function depends on state of HIFSEL
[2:0].
HRD1#
I
A R/W control signal.
Its function depends on state of HIFSEL
[2:0].
HWR0#
I
A R/W control signal.
Its function depends on state of HIFSEL
[2:0].
HWR1#
I
A R/W control signal.
Its function depends on state of HIFSEL
[2:0].
HINT
Tri
It is the interrupt signal.
Polarity is settable.
HIFSEL[2:0]
I
Host interface type select signal
HMUX
I
Host interface bus multiplex (enabled at the reset)
1:Separate bus, 0:Multiplex bus
HINTPOL
I
Host interrupt line polarity select (enabled at the reset)
1:HIGH active, 0:LOW active
HENDIAN
I
Host interface endian select (enabled at the reset)
1:Big Endian, 0:Little Endian
HSIZE
I
Host interface size select (enabled at the reset)
1:8bit, 0:16bit
Tri: 3-state output
When HCS# is LOW, an access port is selected depending on the state of HA [2:0].
Following shows the port
assignment.
(1) When 16-bit interface is selected
HA[2:0]
Access port
00
×
Command port (Write) / Status port (Read)
01
×
Data port
1
××
Flag port
Note: The flag port outputs the same contents to the upper and lower 8 bits.
(2) When 8-bit interface is selected
HA[2:0]
Access port
000
Lower command port (Write) / Lower status port (Read)
001
Upper command port (Write) /Upper status port (Read)
010
Lower data port
011
Upper data port
1
××
Flag port
Note:
When the 8-bit interface is used, data transfer of one time is completed as access is made to both the upper
and lower ports.
The order in accessing the upper and lower ports is optional.
The flag port does not have the
upper or lower port.
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