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参数资料
型号： S1S60000F00A100
元件分类： 微控制器/微处理器
英文描述： 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封装： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP15-100
文件页数： 2/83页
文件大小： 1024K
代理商： S1S60000F00A100
S1S60000 Technical Manual
4
EPSON
Rev.1.5
1.4.2
Pin Functions
Following describes pins used on S1S60000.
Symbol “#” added to a signal name indicates it a negative logic.
Notations such as “[15:0]” indicate that the subject signal comprises two or more signal lines.
For details of
respective pins, refer to Appendix B List of Pin Characteristics.
1.4.2.1
Pin in Power Supply System
Table 1.1
List of Pins used in Power Supply System
Pin name
Pin No.
I/O
Function
VDD
18,32,44,47,61,79,90
-
Built-in logic power supply (
+)
Power pins.
Be sure to supply
+3.3V to every pin.
VSS
9,25,45,52,70,88
-
Power supply (-) GND
Grounding pins.
Be sure to ground every pin.
1.4.2.2
Host Interface Signals
It is the interface used to connect the host CPU.
Every input pin including I/O contains a pull-up resister
enabling 5V input of HCS#, HA [2:0], HD [15:0], HRD0#, HRD1#, HWR0# and HWR1#.
The output is 3.3V
CMOS 3-state output.
Table 1.2
List of Host Interface Signals
Pin name
Pin No.
I/O
Function
HCS#
48
I
Host Chip Select:
It is the host interface access control signal.
Access to the host
interface is enabled as long as this signal remains LOW.
This pin has a built-in pull-up resister enabling to accept 5V input.
HA[2:0]
51,50,49
I
Host Address:
It is the host interface port select signal.
It selects the port to be
accessed while HCS# = LOW.
Following shows the selectable ports.
00
×: Command port (write)/Status port (read)
01
×: Data port (read/write)
1
××: Flag port (read/write)
These pins contain the pull-up resister enabling to accept 5V input.
HA0 is used for switching between the upper and lower bytes when
the 8-bit interface is selected.
It is disabled when the 16-bit
interface is used.
HD[15:0]
69 to62,
60 to 53
I/O
Host Data:
Data signal line of the host interface.
When the 8-bit interface is
selected, HDATA [7:0] alone is enabled and HDATA [15:8] is not
driven.
These pins contain the pull-up resister enabling to accept 5V input.
Output is 3.3V CMOS output.
HRD0#
71
I
HRD1#
72
I
HWR0#
73
I
HWR1#
74
I
Host Read/Host Write:
R/W control signal of the host interface.
Function changes
depending on the HIFSEL[2:0] bit status in the HIFCR register.
For
the detail, refer to “4. Host Interface”.
These pins contain the pull-up resister enabling to accept 5V input.
HINT
75
Tri
Host Interrupt:
Interrupt line from S1S60000 to the host interface.
Causes of
interrupts are identifiable from contents of the flag port.
Polarity of
the interrupt is changeable by changing state of HINTPOL line at the
reset.
Since this signal is 3.3V/3-state output, be sure to externally connect a
pull-up resister when HINTPOL=0 and a pull down resister when
HINTPOL=1.
HIFSEL[2:0]
83,82,78
I
Host Interface Select:
It is the host interface type select signal.
These pins contain the
pull-up resister.
For the detail, refer to “4. Host Interface”.
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