- 您现在的位置：买卖IC网 > PDF目录69326 > S1S60000F00A100 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 PDF资料下载
参数资料
| 型号： | S1S60000F00A100 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP15-100 |
| 文件页数： | 8/83页 |
| 文件大小： | 1024K |
| 代理商： | S1S60000F00A100 |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页
S1S60000 Technical Manual
10
EPSON
Rev.1.5
2.
HARDWARE SPECIFICATIONS
2.1
Core CPU
Seiko Epson original 32 bits microcomputer S1C33240 or equivalent is employed for the core CPU.
ADC,
however, is not built in it.
CPU operating clock, always working identically with the internal bus, is initially set to twice the OSC3.
Setting PSEN bit (11 bit) of GENCR register reduces it to 1/4 clock comparing when it operates normally.
This
arrangement helps reducing operating current.
The inside is processed according to Little Endian.
2.1.1
ROM and Boot Address
S1S60000 contains a 128Kbytes Flash ROM.
After the reset, it is started from 0
×0C00000, namely area 10
Flash ROM area.
Of these 128Kbytes, 127Kbytes are for the system firmware area, while the remaining
1Kbyte is for the user area.
The user area ranges from 0
×C1FC00 to 0×C1FFFF.
Rewriting in the system firmware is done from the debug serial pin and network by using a special tool and
program.
To rewrite in the user area, the debug serial pin or host interface can be used.
Also, to rewrite in the
user area, the debug serial pin or the host interface is used and the host interface command is executed, and it is
not necessary to designate an absolute address.
However, this area can be used only as a data area. This area
cannot store a program for execution.
2.1.2
RAM
S1S60000 contains an 8Kbytes RAM.
Device size of this built-in RAM is 32 bits enabling to read/write data of
a byte, half-word or word in a single cycle.
Since this RAM is exclusively used by S1S60000, user can’t
operate it.
2.2
Peripheral Circuits
Among the peripheral blocks of the built-in core CPU S1C33240, S1S60000 uses the following built-in
peripheral circuits.
For details of respective peripheral circuits, refer to “S1C33 Family ASIC Macro Manual”.
C33 core block
CPU
32-bit RISC type CPU S1C33000
BCU
Bus control unit
ITC
Interrupt controller
CLG
Clock generator
DBG
Functional block for debugging featured with ICD33 (In-Circuit Debugger for S1C33
Family)
C33 peripheral circuits block
Pre-scaler
Used to set the clock for peripheral circuits programmable
16 bits programmable timer
Serial interface
Input/output port
Elapsed timer
C33DMA block
HSDMA (HIGH-speed DMA)
4-channel
The I/O memory map contained S1S60000 is essentially the same as that of S1C33240.
For the detail, refer to
“S1C33240 Technical Manual”.
相关PDF资料 |
PDF描述 |
|---|---|
| S202T01 | TRIGGER OUTPUT SOLID STATE RELAY, 3000 V ISOLATION-MAX |
| S102T01 | TRIGGER OUTPUT SOLID STATE RELAY, 3000 V ISOLATION-MAX |
| S3C4510BXX-QE | 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP208 |
| S3C72E8XX-QX | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP100 |
| S3C72N4XX-QT | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S1S60000F00A300 | 制造商:Epson Electronics America Inc 功能描述:IC NETWORK CONTROLLER |
| S1S60000F00A30B | 制造商:Epson Electronics America Inc 功能描述:IC NETWORK CONTROLLER |
| S1S60000F00A500 | 制造商:Epson Electronics America Inc 功能描述:IC NETWORK CONTROLLER |
| S1S65000F00A100 | 功能描述:IC WEB CAMERA 128-QFP RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| S1S65010 | 制造商:EPSON 制造商全称:EPSON 功能描述:Network Camera Controller with JPEG Encoder |
发布紧急采购，3分钟左右您将得到回复。