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| 型号： | SII3531ACNU |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, QCC48 |
| 封装： | 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48 |
| 文件页数： | 15/81页 |
| 文件大小： | 532K |
| 代理商： | SII3531ACNU |
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PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
22
Direct Command Transfer Method – Host controlled write to Slot
In systems that have the capability to perform burst writes, this is the preferred method of command transfer. Embedded
systems would most likely use this method. LRAM is directly mapped through use of Base Address Register 1, and
appears as a block of memory to the host driver. The host driver writes the PRB contents into the appropriate slot in
LRAM. Ideally, this operation is performed as a single PCI Express transaction. The 5-bit slot number (0-30) is written to
the Command Execution FIFO. The Active bit associated with the selected slot becomes set in the Port Slot Status
register. Note that the Command Fetch FIFO and Command Fetch State Machine are not used for the direct method of
command transfer.
Indirect Command Transfer Method – SiI3531A controlled command transfer
The host driver builds a PRB in host memory, selects a free slot, and writes the physical address of the PRB into the
Activation register corresponding to the selected slot. This causes the SiI3531A to push the 5-bit slot number (0-30) into
the Command Fetch FIFO. The Command Fetch State Machine, while in an idle state, continuously interrogates the
Command Fetch FIFO for a “non-empty” condition. Upon retrieval of a 5-bit slot number from the FIFO, the Command
Fetch State Machine retrieves the physical address of the PRB from the corresponding activation register, sets the Active
bit associated with the selected slot in the Port Slot Status register, and queues a PCI Express read of the PRB into the
associated Slot in LRAM. The Command Fetch State Machine waits for completion of the transfer, pushes the 5-bit slot
number into the Command Execution FIFO, and returns to the idle state, waiting for a non-empty condition in the
Command Fetch FIFO.
The Command Execution State Machine is responsible for directing the flow of the command and response FISes between the
command slot and the serial ATA link, directing the flow of data between PCI Express and the serial ATA link, and posting
completion status to the host. It is also responsible for error handling when exceptions occur in the normal command flow.
Command execution begins when the idle Command Execution State Machine recognizes that the serial ATA bus is in a non-
busy state and the Command Execution FIFO is non-empty. The Command Execution State Machine retrieves the 5-bit slot
number (0-30) from the Command Execution FIFO and uses it to index the command slot in LRAM. The command FIS is
addressed and sent to the serial ATA link to be sent to the device. Control flags in the command slot determine the type of
data transfer. The Command Execution State Machine waits for a response FIS from the device and directs its activities
accordingly. If the received FIS is a data FIS, the DMA address and count are determined by examining the Scatter/Gather
Entries in the PRB and, if necessary, “walking” a Scatter/Gather Table. The DMA address and count are loaded into the DMA
controller and the controller is armed. A DMA activate FIS causes similar behavior, with data flowing from PCI Express to the
Serial ATA link. When the command has completed, the Command Completion bit in the Port Interrupt Status register is set to
reflect the successful completion of the command. If an error occurred, the Command Error bit is set in the Port Interrupt
Status register.
The basic command flow proceeds as follows:
1.
The host builds a 64-byte Port Request Block (PRB) that contains:
The Register- Host to Device FIS to send to the SATA device
Up to two scatter/gather entries to define regions of host memory to be accessed for associated read/write data.
Additional scatter/gather entries may be associated with the command.
Various optional control flags to direct the SiI3531A to perform special processing, to control interrupt assertion,
to vary the normal protocol flow, etc.
2.
The host issues the command to the SiI3531A.
3.
The SiI3531A executes the command, performing all interaction with the SATA device and transferring data between
host memory and the SATA device.
4.
The SiI3531A asserts a PCI Express interrupt to indicate command completion.
5.
The host reads the SiI3531A port slot status to determine which command(s) have completed.
5.3 Data Structures
5.3.1
The Command Slot
Each port within the SiI3531A contains 31 command slots. The slots are numbered 0 through 30. Each command issued by
the host occupies a single command slot. The host decides which slot to use and issues a command to the selected slot. A
command slot occupies 128 bytes within the SiI3531A RAM array and consists of a 64 byte PRB (Port Request Block) and a
64-byte scatter/gather table. The host builds the PRB. It contains the Register-Host To Device FIS to transmit to the attached
SATA device and up to two scatter/gather entries that define host memory regions to be used for any read/write data
associated with the command. If more scatter/gather entries are required to define additional host memory regions, the
SiI3531A will fetch them from host memory as needed. The host may simply append the additional SGT entries to the PRB, or
one of the scatter/gather entries in the PRB may be used to define an SGT (scatter/gather table) that resides in host memory.
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