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参数资料
| 型号： | SII3531ACNU |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, QCC48 |
| 封装： | 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48 |
| 文件页数： | 60/81页 |
| 文件大小： | 532K |
| 代理商： | SII3531ACNU |
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PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
63
6.3.2
Port Slot Status
Address Offset: 1800H
Access Type: Read
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Attention
Slot Status
This register provides the status for the 31 Command Slots for the Serial-ATA port. This register also appears along with the
Port Status register of the other port in Global register space. Reading this register will clear the Command Completion Status
for the port if the Interrupt No Clear on Read bit (bit 3) of the Port Control register is 0. The register bits are defined below.
Bit [31]: Attention (R) – This bit indicates that something occurred in the port that requires the attention of the host.
Other port registers must be examined to determine the origin of the error. This bit is the logical OR of the masked
interrupt conditions reported in the Port Interrupt Status register.
Bit [30:0]: Slot Status (R) – These bits are the Active status bits corresponding to Slot numbers 30 to 0. The Active
status bit is set when a command is transferred to the Slot RAM.
6.3.3
Port Control Set
Address Offset: Set: 1000H
Access Type: Write One To Set
Reset Value: N/A
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
OOB
Bypas
s
Reserved
LED
On
Auto
I
n
te
rl
oc
k
Acc
e
p
t
PM
Enable
Int
e
rlock
A
c
cept
Int
e
rlock
R
e
je
c
t
3
2
-bi
tAc
ti
v
a
ti
on
Scrambl
e
Dis
a
ble
CONT
Dis
a
ble
Transmit
B
IST
R
esume
Pac
ket
Length
LE
D
Dis
a
b
le
Inte
rrupt
NCoR
Port
Init
ializ
e
D
evic
e
R
e
s
e
t
Port
R
e
set
This register is used to direct various port operations. A one written to a bit position sets that bit in the control register.
Bit [31:26,24:16]: Reserved (R). These bits are reserved.
Bit [25]: OOB Bypass (W1S). If this bit is set, the Link will bypass the OOB initialization sequence following a
reset. This bit is reset by Global Reset, and not reset by Port Reset.
Bit [15]: LED On (W1S). This bit turns on the LED Port Activity indicator regardless of the state of LED Disable
(bit 4).
Bit [14]: Auto Interlock Accept (W1S). When this bit is set the link will accept any interlocked FIS reception.
The link will transmit R_OK in response to the received FIS.
Bit [13]: PM Enable (W1S). This bit enables Port Multiplier support.
Bit [12]: Interlock Accept (W1S). This bit is used to signal the link to accept an interlocked FIS reception. The
link will transmit R_OK in response to the received FIS. This bit is self-clearing.
Bit [11]: Interlock Reject (W1S). This bit is used to signal the link to reject an interlocked FIS reception. The
link will transmit R_ERR in response to the received FIS. This bit is self-clearing.
Bit [10]: 32-bit Activation (W1S). When this bit is set to one, a write to the low 32 bits of a Command Activation
register will cause the 32-bit Activation Upper Address register contents to be written to the upper 32 bits of the
Command Activation register and will trigger command execution. When this bit is zero, a write to the upper 32
bits or all 64 bits of a command activation register is required to trigger command execution. This bit is set for
environments that do not address more than 2
32 bytes of host memory.
Bit [9]: Scrambler Disable (W1S). When this bit is set to one, the Link scrambler operation is disabled.
Bit [8]: CONT Disable (W1S). When this bit is set to one, the Link will not generate a CONT following repeated
primitives.
Bit [7]: Transmit BIST (W1S). This bit causes transmission of a BIST FIS.
Bit [6]: Resume (W1S).
Bit [5]: Packet Length (W1S). This bit directs the length of the packet command to be sent for commands with
packet protocol. When this bit is zero, a 12-byte packet will be sent. When this bit is one, a 16-byte packet will
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