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| 型号： | SII3531ACNU |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, QCC48 |
| 封装： | 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48 |
| 文件页数： | 30/81页 |
| 文件大小： | 532K |
| 代理商： | SII3531ACNU |
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PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
36
i.
Issue Identify Packet Device command to get device specific parameters
ii.
While drive is not ready and timeout has not expired:
1.
Issue Test unit ready PACKET command
2.
If the command completes successfully, drive is ready
3.
Else, if command error indicates Device error condition due to drive not ready, write
Initialize Port to the Port Control Register (port*0x2000)+0x1000, bit 2)
4.
Wait until Port Ready in Port Status Register (Port offset (port*0x2000)+0x1000, bit 31) is
one. If desired, an interrupt may be armed in the Port Interrupt Set Register (bit 2). Any
change in Port Ready state will assert an interrupt.
iii.
Drive is ready for use. Issue appropriate Set Features, Set Read Multiple commands as needed.
j.
If the signature is 0x00000101, then the attached device is a disk drive.
i.
Issue Identify Device command to get device specific parameters
ii.
Drive is ready for use. Issue appropriate Set Features, Set Read Multiple commands as needed.
5.4.6
Interrupts and Command Completion
Each port of the SiI3531A produces a single interrupt, which is an accumulation of various possible interrupt events. In its
default mode, the SiI3531A combines the interrupts from the ports into a single interrupt that may be used either for INTA
emulation or for a Message Signaled Interrupt. In certain embedded environments, it might be desirable for each port to
generate an independent interrupt. Software may configure each port to direct its interrupt to one of four emulated interrupts.
The Interrupt Steering field in the Port Interrupt Enable Set/Clear register (Port offset 0x1010/1014, bit [31:30]) is used to direct
the port interrupt. By default, this field is set to a value of zero, indicating that the interrupt is directed to INTA. The register
may be set to one of four values:
Interrupt Steering Value
Interrupt
0
INTA
1
INTB
2
INTC
3
INTD
Table 5-11 Interrupt Steering
5.4.7
Interrupt Sources
Figure 5-3 on page 38 depicts a logical representation of the interrupt routing for the SiI3531A. For Each port, the possible
interrupt causes are:
Command Completion. Indicates that one or more commands have successfully completed. This interrupt is
cleared in one of two ways, dependent upon the state of Interrupt NCoR (Port Control Register, bit 3). Reading
the port Slot Status Register will clear this interrupt condition if Interrupt NCoR is zero. Writing a one to bit 0 or
16 of the port Interrupt Status Register will clear this interrupt condition if Interrupt NCoR is one. This interrupt is
enabled or disabled with the corresponding bit in the port Interrupt Enable Set/Clear Register.
Command Error. Indicates that a command did not complete successfully. The port Command Error register will
contain an error code indicating the actual cause of failure. When this bit is set, Port Ready will be set to zero
and no additional commands will be processed until the port is initialized by one of the reset methods and Port
Ready is asserted. Writing a one to bit 1 or 17 of the port Interrupt Status Register clears this interrupt condition.
This interrupt is enabled or disabled with the corresponding bit in the port Interrupt Enable Set/Clear Register.
Port Ready. Indicates that the Port Ready state has changed from zero to one. Writing a one to bit 2 or 18 of
the port Interrupt Status Register clears this interrupt condition. This interrupt is enabled or disabled with the
corresponding bit in the port Interrupt Enable Set/Clear Register.
Power Management Change. Indicates that the port power management state has been modified. The current
power management state can be determined by reading the port SStatus Register. Writing a one to bit 3 or 19 of
the port Interrupt Status Register clears this interrupt condition. This interrupt is enabled or disabled with the
corresponding bit in the port Interrupt Enable Set/Clear Register.
PHY Ready Change. Indicates that the PHY state has changed from Not Ready to Ready or from Ready to Not
Ready. The current PHY state can be determined by reading the port SStatus Register. Writing a one to bit 4 or
20 of the port Interrupt Status Register clears this interrupt condition. This interrupt is enabled or disabled with
the corresponding bit in the port Interrupt Enable Set/Clear Register.
COMWAKE Received. Indicates that a COMWAKE OOB signal has been decoded on the receiver. Writing a
one to bit 5 or 21 of the port Interrupt Status Register clears this interrupt condition. This interrupt is enabled or
disabled with the corresponding bit in the port Interrupt Enable Set/Clear Register.
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