PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
58
6.2.3
Global Interrupt Status
Address Offset: 44H
Access Type: Read/Write 1 Clear
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Port
Interrupt
This register is used to determine the status of various chip functions.
Bit [31:1]: Reserved (R). This bit field is reserved and returns zeroes when read.
Bit [0]: Port Interrupt Status (R/W1C). This bit, when set to one, indicates that the port has an interrupt condition
pending. Writing a 1 to this bit clears the Command Completion Interrupt Status, but not other interrupt sources.
6.2.4
PHY Configuration
Address Offset: 48H
Access Type: Read/Write
Reset Value: 0x0000_2C40
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
PHY Config
The PHY Configuration register is reset to 0x00002C40. These bits should not be changed from their defaults as erratic
operation may result (including bits identified as Reserved).
6.2.5
BIST Control Register
Address Offset: 50H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
B
ISTenable
BISTpatsel
Reserved
BISTrun
This register is used to control Data Loopback BIST.
Bit [31]: BISTenable (R/W) – This bit enables the data paths for running data loopback BIST.
Bit [30]: BISTpatsel (R/W) – This bit selects whether a repeating pattern (supplied from the BIST Pattern
register) or a pseudorandom pattern is used for running data loopback BIST. Setting the bit to 1 selects the
repeating pattern.
Bit [29:01]: Reserved (R). These bits are reserved and return zeros on a read.
Bit [00]: BISTrun (R/W). This bit enables the transmission of loopback data.