参数资料
型号: SII3531ACNU
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, QCC48
封装: 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48
文件页数: 47/81页
文件大小: 532K
代理商: SII3531ACNU
PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
51
6.1.19 Device Status and Control
Address Offset: 78H
Access Type: Read/Write/Write 1 to Clear
Reset Value: 0x0000_2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Trans
P
e
nding
AUX
P
o
we
r
Uns
up
Re
q
De
t
Fa
ta
lE
rror
De
t
Non-Fatal
Error
Corr
Error
Det
R
eser
ved
Max Read
Request
Size
EnSnp
Not
Req
A
u
x
Pwr
PM
En
Phntm
Fnc
En
Ext
Tag
Fld
En
Max
Payload
Size
En
Rlxd
Ord
Uns
R
e
q
Re
p
E
n
Fatal
Err
Rep
En
NonFtl
Err
Rep
En
Corr
Err
Rep
En
Bit [31:22,15]: Reserved (R) – These bits are reserved and return zero on a read.
Bit [21]: Trans Pending (R) – Transactions Pending.
Bit [20]: AUX Power (R) – AUX Power Detected. This bit is hardwired to 0.
Bit [19]: Unsup Req Det (R/W1C) – Unsupported Request Detected.
Bit [18]: Fatal Error Det (R/W1C) – Fatal Error Detected.
Bit [17]: Non-Fatal Error (R/W1C) – Non-Fatal Error Detected.
Bit [16]: Corr Error Det (R/W1C) – Correctable Error Detected.
Bit [14:12]: Max Read Request Size (R/W) – Allowable values are 000B to 011B (128 to 1024 bytes). Default is
010B (512 bytes).
Bit [11]: EnSnp Not Req (R) – Enable No Snoop. This bit is hardwired to 0.
Bit [10]: Aux Pwr PM En (R) – Auxiliary Power PM Enable. This bit is hardwired to 0.
Bit [09]: Phntm Fnc En (R) – Phantom Functions Enable. This bit is hardwired to 0.
Bit [08]: Ext Tag Fld En (R) – Extended Tag Field Enable. This bit is hardwired to 0.
Bit [07:05]: Max Payload Size (R/W) – Allowable values are 000B to 011B (128 to 1024 bytes). Default is 000B
(128 bytes).
Bit [04]: En Rlxd Ord (R) – Enable Relaxed Ordering. This bit field is hardwired to 0.
Bit [03]: UnsReq Rep En (R/W) – Unsupported Request Reporting Enable.
Bit [02]: Fatal Err Rep En (R/W) – Fatal Error Reporting Enable.
Bit [01]: NonFtl Err Rep En (R/W) – Non-Fatal Error Reporting Enable.
Bit [00]: Corr Err Rep En (R/W) – Correctable Error Reporting Enable.
6.1.20 Link Capabilities
Address Offset: 7CH
Access Type: Read Only
Reset Value: 0x0003_F411
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Port Number
Reserved
L1 Exit
Latency
L0s Exit
Latency
ASPM
Support
Maximum Link Width
Maximum Link
Speed
Bit [31:24]: Port Number (R) – This bit field is hardwired to 00H.
Bit [23:18]: Reserved (R) – These bits are reserved and return zero on a read.
Bit [17:15]: L1 Exit Latency (R) – This bit field is hardwired to 111B.
Bit [14:12]: L0s Exit Latency (R) – This bit field is hardwired to 111B.
Bit [11:10]: ASPM Support (R) – This bit field is hardwired to 01B.
Bit [09:04]: Maximum Link Width (R) – This bit field is hardwired to 000001B.
Bit [03:00]: Maximum Link Speed (R) – This bit field is hardwired to 0001B.
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