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参数资料
| 型号： | SII3531ACNU |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, QCC48 |
| 封装： | 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48 |
| 文件页数： | 74/81页 |
| 文件大小： | 532K |
| 代理商： | SII3531ACNU |
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PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
76
6.3.22 SError
Address Offset: 1F08H
Access Type: Read/Write 1 Clear
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
R
X
F
T
S
H
C
D
B W
I
N
RRRR
EP
CT
R
MI
DIAG
ERR
This register is the SError register as defined by the Serial ATA specification (section 10.1.2).
Bit [31:16]: DIAG (R/W1C) – This field contains bits defined as shown in the following table. Writing a 1 to the
register bit clears the B, C, F, N, H, W, and X bits. Writing a 1 to the corresponding bits in the Port Interrupt
Status register also clears the F, N, W, and X bits.
The B, C, and H bits operate independently of the
corresponding error counter registers; if the error counters are used, these bits should be ignored.
Bit
Definition
Description
B
10b to 8b decode error
Latched decode error or disparity error from the Serial ATA PHY
C
CRC error
Latched CRC error from the Serial ATA PHY
D
Disparity error
N/A, always 0; this error condition is combined with the decode
error and reported as B error
F
Unrecognized FIS type
Latched Unrecognized FIS error from the Serial ATA Link
I
PHY Internal error
N/A, always 0
N
PHYRDY change
Indicates a change in the status of the Serial ATA PHY
H
Handshake error
Latched Handshake error from the Serial ATA PHY
R
Reserved
Always 0
S
Link Sequence error
N/A, always 0
T
Transport state transition error
N/A, always 0
W
ComWake
Latched ComWake status from the Serial ATA PHY
X
Device Exchanged
Latched ComInit status from the Serial ATA PHY
Table 6-10 SError Register Bits (DIAG Field)
Bit [15:00]: ERR – This field is not implemented; all bits are always 0.
6.3.23 SActive
Address Offset: 1F0CH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Active bits
This register provides indirect access of the Port Device QActive registers (see section 6.3.18 for description). It contains
the Active bits used to determine the activity of native queued commands for the selected Port Multiplier port (selection in
SControl). A one in any bit position indicates that the corresponding command is still active in the device.
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