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参数资料
| 型号： | SII3531ACNU |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, QCC48 |
| 封装： | 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48 |
| 文件页数： | 43/81页 |
| 文件大小： | 532K |
| 代理商： | SII3531ACNU |
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PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
48
6.1.12 Power Management Capability
Address Offset: 54H
Access Type: Read Only
Reset Value: 0x0622_5C01
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PME Support
PPM
D2
Support
PPM
D1
Support
Auxiliary
Current
Dev
Spe
c
ia
lInit
R
eser
v
ed
PM
E
C
lock
PPM Rev
Next Capability Pointer
Capability ID
This register defines the power management capabilities associated with the PCI bus. The register bits are defined below.
Bit [31:27]: PME Support (R) – Power Management Event Support. This bit field is hardwired to 00H; the
SiI3531A does not support PME.
Bit [26]: PPM D2 Support (R) – PCI Power Management D2 Support. This bit is hardwired to 1.
Bit [25]: PPM D1 Support (R) – PCI Power Management D1 Support. This bit is hardwired to 1.
Bit [24:22]: Auxiliary Current (R) – Auxiliary Current. This bit field is hardwired to 000B.
Bit [21]: Dev Special Init (R) – Device Special Initialization. This bit is hardwired to 1 to indicate that the
SiI3531A requires special initialization.
Bit [20]: Reserved (R). This bit is reserved and returns zero on a read.
Bit [19]: PME Clock (R) – Power Management Event Clock. This bit is hardwired to 0.
Bit [18:16]: PPM Rev (R) – PCI Power Management Revision. This bit field is hardwired to 010B to indicate
compliance with the PCI Power Management Interface Specification revision 1.1.
Bit [15:08]: Next Capability Pointer (R) – PCI Next Capability Pointer. This bit field is hardwired to 5CH to point
to the 2
nd Capabilities register, the MSI Capability.
Bit [07:00]: Capability ID (R) – PCI Capability ID. This bit field is hardwired to 01H to indicate that this is a PCI
Power Management Capability.
6.1.13 Power Management Control + Status
Address Offset: 58H
Access Type: Read/Write
Reset Value: 0x0800_2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PPM Data
Reserved
PM
E
St
at
us
PPM
D
a
ta
S
c
al
e
PPM Data Sel
PM
E
Ena
Reserved
PPM
Power
St
at
e
This register defines the power management capabilities associated with the PCI bus. The register bits are defined below.
Bit [31:24]: PPM Data (R) – PCI Power Management Data. This bit field is hardwired to 0x08 to indicate a
power consumption of 800 milliwatts.
Bit [23:16]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [15]: PME Status (R) – PME Status. This bit is hardwired to 0. The SiI3531A does not support PME.
Bit [14:13]: PPM Data Scale (R) – PCI Power Management Data Scale. This bit field is hardwired to 01B to
indicate a scaling factor of 100 milliwatts.
Bit [12:09]: PPM Data Sel (R/W) – PCI Power Management Data Select. This bit field is set by the system to
indicate which data field is to be reported through the PPM Data bits (although current implementation hardwires
the PPM Data to indicate 1.2 Watt).
Bit [08]: PME Ena (R) – PME Enable. This bit is hardwired to 0. The SiI3531A does not support PME.
Bit [07:02]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [01:00]: PPM Power State (R/W) – PCI Power Management Power State. This bit field is set by the system
to dictate the current Power State: 00 = D0 (Normal Operation), 01 = D1, 10 = D2, and 11 = D3 (Hot).
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