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参数资料
| 型号： | SII3531ACNU |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, QCC48 |
| 封装： | 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48 |
| 文件页数： | 46/81页 |
| 文件大小： | 532K |
| 代理商： | SII3531ACNU |
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PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
50
6.1.17 PCI Express Capability
Address Offset: 70H
Access Type: Read Only
Reset Value: 0x0011_0010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
R
e
ser
ved
Interrupt Message
Number
R
e
ser
ved
Device Type
Version
Next Capability Pointer
Capability ID
Bit [31:30,24]: Reserved (R) – These bits are reserved and return zero on a read.
Bit [29:25]: Interrupt Message Number (R) – This bit field is hardwired to 0.
Bit [23:20]: Device Type (R) – This bit field is hardwired to 0001B to indicate a PCI Express Legacy Endpoint
device.
Bit [19:16]:
Version (R) – This bit field is hardwired to 01H to indicate compliance with the PCI Express
Specification revision 1.0a.
Bit [15:08]: Next Capability Pointer (R) – PCI Next Capability Pointer. This bit field is hardwired to 00H (this is
the last capability).
Bit [07:00]: Capability ID (R) – PCI Capability ID. This bit field is hardwired to 10H to indicate that this is a PCI
Express Capability.
6.1.18 Device Capabilities
Address Offset: 74H
Access Type: Read Only
Reset Value: 0x0000_8003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Slot Power
R
e
ser
ved
R
o
le-
b
ased
Err
Re
p
Pwr
Indic
a
tor
Atten
Indicator
Atte
n
Button
L1
Latency
L0s
Latency
Ext
Tag
Sup
Phant
o
m
Functions
Max
Payload
Bit [31:28,17:16]: Reserved (R) – These bits are reserved and return zero on a read.
Bit [27:18]: Slot Power (R) – Captured Slot Power Limit Value and Limit Scale. This bit field is hardwired to 0.
Bit [15]: Role-based Err Rep (R) – Role-based Error Reporting. This bit is hardwired to 1.
Bit [14]:
Pwr Indicator (R) – Power Indicator Present.
This bit is set if Hot Plug is enabled (HPLE_N pin
connected to 0) to indicate the presence of the Hot Plug Power Indicator.
Bit [13]: Atten Indicator (R) – Attention Indicator Present. This bit is set if Hot Plug is enabled (HPLE_N pin
connected to 0) to indicate the presence of the Hot Plug Attention Indicator.
Bit [12]:
Atten Button (R) – Attention Button Present.
This bit is set if Hot Plug is enabled (HPLE_N pin
connected to 0) to indicate the presence of the Hot Plug Attention switch (connected to the HPL_N pin).
Bit [11:09]: L1 Latency (R) – This bit field is hardwired to 000B.
Bit [08:06]: L0s Latency (R) – This bit field is hardwired to 000B.
Bit [05]: Ext Tag Sup (R) – Extended Tag Field Supported. This bit is hardwired to 0.
Bit [04:03]: Phantom Functions (R) – This bit field is hardwired to 0.
Bit [02:00]: Max Payload (R) – Max_Payload_Size Supported. This bit field is hardwired to 011B to indicate that
a maximum 1024-byte payload is supported.
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