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| 型号： | SII3531ACNU |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, QCC48 |
| 封装： | 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48 |
| 文件页数： | 3/81页 |
| 文件大小： | 532K |
| 代理商： | SII3531ACNU |
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PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
11
2.2 SATA Interface Timing Specifications
Limits
Symbol
Parameter
Condition
Min
Typ
Max
Unit
TTX_RISE_FALL
Rise and Fall time at
transmitter
20%-80% at Gen 1
20%-80% at Gen 2
100
67
273
136
ps
TTX_TOL_FREQ
Tx Frequency Long Term
Stability
-350
+350
ppm
Table 2-5 SATA Interface Timing Specifications
2.3 SATA Interface Transmitter Output Jitter Characteristics
Limits
Symbol
Parameter
Condition
Min
Typ
Max
Unit
TJ5UI_15G
Total Jitter, Data-Data 5UI
Measured at Tx output pins
peak to peak phase variation
Random data pattern
80
ps
DJ5UI_15G
Deterministic Jitter, Data-
Data 5UI
Measured at Tx output pins
peak to peak phase variation
Random data pattern
50
ps
TJ250UI_15G
Total Jitter, Data-Data
250UI
Measured at Tx output pins
peak to peak phase variation
Random data pattern
85
ps
DJ250UI_15G
Deterministic Jitter, Data-
Data 250UI
Measured at Tx output pins
peak to peak phase variation
Random data pattern
55
ps
Table 2-6 SATA Interface Transmitter Output Jitter Characteristics, 1.5 Gb/s
Limits
Symbol
Parameter
Condition
Min
Typ
Max
Unit
TJfBAND/10_3G
Total Jitter, fC3dB=fBAUD/10
Measured at SATA Compliance
Point
clock pattern
Load = LL Laboratory Load
70*
ps
DJfBAND/10_3G
Deterministic Jitter,
fC3dB=fBAUD/10
Measured at SATA Compliance
Point
clock pattern
Load = LL Laboratory Load
45*
ps
TJfBAND/500_3G
Total Jitter, fC3dB=fBAUD/500
Measured at SATA Compliance
Point
Random data pattern
Load = LL Laboratory Load
80
ps
DJfBAND/500_3G
Deterministic Jitter,
fC3dB=fBAUD/500
Measured at SATA Compliance
Point
Random data pattern
Load = LL Laboratory Load
55
ps
Table 2-7 SATA Interface Transmitter Output Jitter Characteristics, 3 Gb/s
* With fC3dB=fBAUD/10 bandwidth, jitter analysis algorithm provided by oscilloscope manufacture requires full transition density
which is clock pattern. A series resistor of 75ohms should be populated close to the VDDX pin
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