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| 型号： | SII3531ACNU |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, QCC48 |
| 封装： | 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48 |
| 文件页数： | 23/81页 |
| 文件大小： | 532K |
| 代理商： | SII3531ACNU |
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PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
3
Table of Contents
1
Overview ...........................................................................................................................................8
1.1
Features ..................................................................................................................................................... 8
1.1.1
Overall Features ...................................................................................................................................................8
1.1.2
PCI Express Features ..........................................................................................................................................8
1.1.3
Serial ATA Features .............................................................................................................................................8
1.2
References ................................................................................................................................................. 8
2
Electrical Characteristics ................................................................................................................9
2.1
Device Electrical Characteristics ............................................................................................................ 9
2.2
SATA Interface Timing Specifications .................................................................................................. 11
2.3
SATA Interface Transmitter Output Jitter Characteristics.................................................................. 11
2.4
PCI Express Interface Timing Specifications....................................................................................... 12
2.5
PCI Express Interface Transmitter Output Jitter Characteristics ...................................................... 12
2.6
XTALI Requirements............................................................................................................................... 12
2.7
Power Supply Noise Requirements ...................................................................................................... 13
3
Pin Definition ..................................................................................................................................14
3.1
SiI3531A Pin Listing................................................................................................................................ 14
3.2
SiI3531A Pin Diagrams ........................................................................................................................... 15
3.3
SiI3531A Pin Descriptions...................................................................................................................... 15
3.3.1
PCI Express Pins ...............................................................................................................................................15
3.3.2
LED / Hot Plug pins ............................................................................................................................................16
3.3.3
Serial ATA Signals..............................................................................................................................................16
3.3.4
NC Pins ..............................................................................................................................................................16
3.3.5
Power/Ground Pins ............................................................................................................................................17
4
Package Drawing............................................................................................................................18
5
Programming Model.......................................................................................................................20
5.1
SiI3531A Block Diagram ......................................................................................................................... 20
5.2
SiI3531A S-ATA Port Block Diagram..................................................................................................... 21
5.3
Data Structures ....................................................................................................................................... 22
5.3.1
The Command Slot.............................................................................................................................................22
5.3.2
The Scatter/Gather Entry (SGE).........................................................................................................................23
5.3.3
The Scatter/Gather Table (SGT) ........................................................................................................................24
5.3.4
The Port Request Block (PRB) ...........................................................................................................................24
5.3.5
The PRB Control Field........................................................................................................................................26
5.3.6
The PRB Protocol Override Field .......................................................................................................................27
5.3.7
Standard ATA Command PRB Structure............................................................................................................28
5.3.8
PACKET Command PRB Structure....................................................................................................................30
5.3.9
Soft Reset PRB Structure...................................................................................................................................31
5.3.10
External Command PRB Structure .....................................................................................................................32
5.3.11
Interlocked Receive PRB Structure ....................................................................................................................33
5.4
Operation ................................................................................................................................................. 34
5.4.1
Command Issuance............................................................................................................................................34
5.4.2
Reset and Initialization .......................................................................................................................................34
5.4.3
Port Ready .........................................................................................................................................................35
5.4.4
Port Reset Operation..........................................................................................................................................35
5.4.5
Initialization Sequence........................................................................................................................................35
5.4.6
Interrupts and Command Completion.................................................................................................................36
5.4.7
Interrupt Sources ................................................................................................................................................36
5.4.8
Command Completion – The Slot Status Register .............................................................................................39
5.4.9
The Attention Bit .................................................................................................................................................40
5.4.10
Interrupt Service Procedure................................................................................................................................40
5.4.11
Interrupt No Clear on Read ................................................................................................................................40
5.4.12
Error Processing.................................................................................................................................................40
5.4.13
Error recovery procedures..................................................................................................................................41
6
Register Definitions .......................................................................................................................43
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