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参数资料
| 型号： | SII3531ACNU |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, QCC48 |
| 封装： | 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48 |
| 文件页数： | 63/81页 |
| 文件大小： | 532K |
| 代理商： | SII3531ACNU |
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PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
66
Bit [18/2]:
Port Ready (W1C).
This bit indicates that the port has become ready to accept and execute
commands. This status indicates that Port Ready (bit 31 in the Port Status register) has made a 0 to 1 transition.
Clearing this status does not change the Port Ready bit in the Port Status register and this status is not set
subsequently until the Port Ready bit changes state.
Bit [17/1]: Command Error (W1C). This bit indicates that an error occurred during command execution. The
error type can be determined via the port error register.
Bit [16/0]:
Command Completion (W1C).
This bit indicates that one or more commands have completed
execution.
6.3.7
Port Interrupt Enable Set / Port Interrupt Enable Clear
Address Offset: 1010H / 1014H
Access Type: Read/Write 1 Set/Write 1 Clear
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Interrupt
St
eering
Reserved
S
DB
Notify
Reserved
D
evEx
c
hg
U
n
recFIS
C
o
mwake
PhyR
dyC
h
g
PM
Change
Port
R
e
ady
Command
Error
Cmd
Comple
tion
The Interrupt Enable register is controlled by these registers. Writing to the Interrupt Enable Set register sets the Interrupt
Enable bits; the enable bit is set for each corresponding bit to which a 1 is written. Writing to the Interrupt Enable Clear
register clears the Interrupt Enable bits; the enable bit is cleared for each corresponding bit to which a 1 is written. The
Interrupt Enable register may be read at either address offset.
Note that bits 8, 9, and 10 do not have an enable bit; the corresponding interrupts are enabled by corresponding threshold
registers.
Bit [31:30]: Interrupt Steering (R/W). This bit field specifies which one of the four interrupts is to be used for
interrupts from this port. INTA is selected by 00B; INTB by 01B; INTC by 10B; and INTD by 11B.
Bit [29:12,10:8]: Reserved (R). These bits are reserved and return zeros on a read.
Bit [11,7:0]: Interrupt Enables (R/W1S/W1C). These bits are the interrupt enables for the corresponding bits of
the Interrupt Status register.
6.3.8
32-bit Activation Upper Address
Address Offset: 101CH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Upper Address
This register contains the 32-bit value written to the upper half of the Command Activation register when the lower half of that
register is written and the 32-bit Activation control bit (bit 10) is set in the Port Control register.
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