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参数资料
| 型号： | SII3531ACNU |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, QCC48 |
| 封装： | 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48 |
| 文件页数： | 75/81页 |
| 文件大小： | 532K |
| 代理商： | SII3531ACNU |
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PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
77
6.3.24 SNotification
Address Offset: 1F10H
Access Type: Read/Write 1 to Clear
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Notify bits
This register reports the devices that have sent a Set Device Bits FIS with the Notification bit set.
Bit [31:16]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [15:00]: Notify bits (R/W1C) – These 16 bits correspond to the 16 possible devices connected to a Port
Multiplier on this port.
6.4 Internal Register Space – Base Address 2
These registers are 32-bits wide and provide Indirect Register Access to the registers of the SiI3531A. Access to this register
space is through the PCI I/O space.
Address Offset
Register Name
00H
Global Register Offset
04H
Global Register Data
08H
Port Register Offset
0CH
Port Register Data
Table 6-11 SiI3531A Internal Register Space – Base Address 2
6.4.1
Global Register Offset
Address Offset: 00H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Dword Offset
00
This register provides indirect addressing of a Global Register otherwise accessible directly via Base Address Register 0. The
Dword address offset for an indirect access is in bits 6 to 2; bits 31 to 7, 1, and 0 are reserved and should always be 0.
Indirect access is not allowed to the Global registers at offsets 0x78 through 0x7F (Configuration register indirect access).
6.4.2
Global Register Data
Address Offset: 04H
Access Type: Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
As defined for indirectly accessed register
This register provides the indirect access addressed by the Global Register Offset register.
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