- 您现在的位置：买卖IC网 > PDF目录69541 > W9725G6IB-18 (WINBOND ELECTRONICS CORP) 16M X 16 DDR DRAM, 0.35 ns, PBGA84 PDF资料下载
参数资料
| 型号： | W9725G6IB-18 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 16M X 16 DDR DRAM, 0.35 ns, PBGA84 |
| 封装： | 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84 |
| 文件页数： | 16/69页 |
| 文件大小： | 1644K |
| 代理商： | W9725G6IB-18 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页
PRELIMINARY W9725G6IB
Publication Release Date:Nov. 14, 2008
- 23 -
Revision P04
7.3.10. No-Operation Command
(
CS = "L", RAS = "H", CAS = "H", WE = "H", CKE, BA0, BA1, A0 to A12 = Don’t Care)
The No-Operation command simply performs no operation (same command as Device Deselect).
7.3.11. Device Deselect Command
(
CS = "H", RAS , CAS , WE , CKE, BA0, BA1, A0 to A12 = Don’t Care)
The Device Deselect command disables the command decoder so that the
RAS , CAS , WE and
Address inputs are ignored. This command is similar to the No-Operation command.
7.4. Read and Write access modes
The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will
initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is
strictly restricted to specific segments of the page length.
The page length of 1024 is divided into 256 or 128 uniquely addressable boundary segments
depending on burst length, 256 for 4 bit burst, 128 for 8 bit burst respectively. A 4-bit or 8-bit burst
operation will occur entirely within one of the 256 or 128 groups beginning with the column address
supplied to the device during the Read or Write Command (CA0-CA9, CA11). The second, third and
fourth access will also occur within this group segment. However, the burst order is a function of the
starting address, and the burst sequence.
A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting.
However, in case of BL = 8 setting, two cases of interrupt by a new burst access are allowed, one
reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundary
respectively. The minimum
CAS to CAS delay is defined by tCCD, and is a minimum of 2 clocks for
read or write cycles.
7.4.1.
Posted CAS
Posted
CAS operation is supported to make command and data bus efficient for sustainable
bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a
CAS read or write
command to be issued immediately after the
RAS bank activate command (or any time during the
RAS - CAS -delay time, tRCD, period). The command is held for the time of the Additive Latency (AL)
before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the
CAS Latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin,
then AL (greater than 0) must be written into the EMR (1). The Write Latency (WL) is always defined
as RL -1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS
Latency (RL = AL + CL). Read or Write operations using AL allow seamless bursts. (Example timing
waveforms refer to 10.11 and 10.12 seamless burst read/write operation diagram in Chapter 10)
7.4.1.1. Examples of posted CAS operation
Examples of a read followed by a write to the same bank where AL = 2 and where AL = 0 are shown
in Figures 14 and 15, respectively.
相关PDF资料 |
PDF描述 |
|---|---|
| W9864G6EB-7 | 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA60 |
| WE128K8200CQ | 128K X 8 EEPROM 5V MODULE, 200 ns, CDIP32 |
| WED9LC6816V1512BI | SPECIALTY MEMORY CIRCUIT, PBGA153 |
| WS128K32-35G2TMEA | 128K X 32 MULTI DEVICE SRAM MODULE, 35 ns, CQFP68 |
| WS128K32-55G2TIE | 128K X 32 MULTI DEVICE SRAM MODULE, 55 ns, CQFP68 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W9725G6IB-25 | 功能描述:IC DDR2-800 SDRAM 256MB 84-WBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.173"，4.40mm 宽） 供应商设备封装:8-MFP 包装:带卷 (TR) |
| W9725G6JB | 制造商:WINBOND 制造商全称:Winbond 功能描述:4M ? 4 BANKS ? 16 BIT DDR2 SDRAM |
| W9725G6JB-25 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 256M-Bit 16Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:512MB DDRII |
| W9725G6JB25I | 功能描述:IC DDR2 SDRAM 256MBIT 84WBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN（2x3） 包装:管件 产品目录页面:1445 (CN2011-ZH PDF) |
| W9725G6KB-18 | 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
发布紧急采购，3分钟左右您将得到回复。