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| 型号： | W9725G6IB-18 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 16M X 16 DDR DRAM, 0.35 ns, PBGA84 |
| 封装： | 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84 |
| 文件页数： | 3/69页 |
| 文件大小： | 1644K |
| 代理商： | W9725G6IB-18 |
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PRELIMINARY W9725G6IB
Publication Release Date:Nov. 14, 2008
- 11 -
Revision P04
A[2:0] with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR
SDRAM. Burst address sequence type is defined by A3, CAS Latency is defined by A[6:4]. The DDR2
does not support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must
be set to LOW for normal MRS operation. Write recovery time WR is defined by A[11:9]. Refer to the
table for specific codes.
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
PD
WR
DLL
BT
CAS Latency
Burst Length
TM
A8
0
1
DLL Reset
No
Yes
BA1
BA0
0
1
0
1
MRS mode
MR
EMR (1)
EMR (2)
EMR (3)
A12
1
0
Active power down exit time
Fast exit (use tXARD)
Slow exit (use tXARDS)
Burst Length
Address Field
Mode Register
Write recovery for Auto-precharge
CAS Latency
A6
0
1
A5
0
1
0
1
A4
0
1
0
1
0
1
0
Latency
Reserved
3
4
5
7
6
Reserved
A2
0
A1
1
A0
0
1
BL
4
8
A11
0
1
A10
0
1
0
1
A9
0
1
0
1
0
1
0
WR *
Reserved
2
3
4
5
6
8
7
A7
0
1
Mode
Normal
Test
A3
0
1
Burst Type
Sequential
Interleave
0
D
R
2
-6
6
7
(-
3
)
D
R
2
-8
0
(-
2
5
)
D
R
2
-1
0
6
(-
1
8
)
D
R
2
-8
0
(-
2
5
)
D
R
2
-1
0
6
(-
1
8
)
D
R
2
-6
6
7
(-
3
)
Note:
1. WR (write recovery for Auto-precharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock
cycles is calculated by dividing tWR (in nS) by tCK (in nS) and rounding up to the next integer (WR[cycles] = RU{ tWR[nS] /
tCK [nS] }, where RU stands for round up). The mode register must be programmed to this value. This is also used with tRP to
determine tDAL.
Figure 2
—
—Mode Register Set (MRS)
7.2.2.
Extend Mode Register Set Commands (EMRS)
7.2.2.1. Extend Mode Register Set Command (1), EMR (1)
(
CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L", A0 to A12 = Register data)
The extended mode register (1) stores the data for enabling or disabling the DLL, output driver
strength, additive latency, ODT,
DQS disable, OCD program. The default value of the extended
mode register (1) is not defined, therefore the extended mode register (1) must be programmed during
initialization for proper operation. The DDR2 SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register (1). The mode register set command
cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (1).
Extended mode register (1) contents can be changed using the same command and clock cycle
requirements during normal operation as long as all banks are in the precharge state. A0 is used for
DLL enable or disable. A1 is used for enabling a reduced strength output driver. A[5:3] determines the
additive latency, A[9:7] are used for OCD control, A10 is used for
DQS disable. A2 and A6 are used
for ODT setting.
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