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| 型号： | W9725G6IB-18 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 16M X 16 DDR DRAM, 0.35 ns, PBGA84 |
| 封装： | 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84 |
| 文件页数： | 42/69页 |
| 文件大小： | 1644K |
| 代理商： | W9725G6IB-18 |
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PRELIMINARY W9725G6IB
Publication Release Date:Nov. 14, 2008
- 47 -
Revision P04
Note:
1. If refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid READ
can be executed.
2. This is an optional feature. For detailed information, please refer to “operating temperature condition” chapter 9.2 in this
data sheet.
3. Min. (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device.
4. tCKE min of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the
valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + 2 x tCK + tIH.
5. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency.
6. tDAL = WR + RU{ tRP[nS] / tCK[nS] }, where RU stands for round up. WR refers to the tWR parameter stored in the MRS.
For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the
application clock period.
Example: For DDR2-533 at tCK = 3.75nS with WR programmed to 4 clocks.
tDAL = 4 + (15 nS / 3.75 nS) clocks = 4 + (4) clocks = 8 clocks.
7. tWTR is at least two clocks (2 * tCK) independent of operation frequency.
8. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing that the tRTP and tRAS(min) have
been satisfied.
9. The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter,
but system performance (bus turnaround) will degrades accordingly.
10. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as
well as output Slew Rate mismatch between DQS / DQS and associated DQ in any given cycle.
11. The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output
is no longer driving (tHZ, tPRST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time
windows as valid data transitions. These parameters are verified by design and characterization, but not subject to
production test.
12. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active
power down exit timing. tXARDS is expected to be used for slow active power down exit timing.
13. AL = Additive Latency.
14. ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time
max. is when the ODT resistance is fully on. Both are measure from tAOND.
15. ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max. is when the bus is in
high impedance. Both are measured from tAOFD.
16. The clock frequency is allowed to change during Self Refresh mode or precharge power-down mode. In case of clock
frequency change during precharge power-down, a specific procedure is required as described in Chapter 7.10.
17. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified. ODT is
disabled for all measurements that are not ODT-specific.
9.12. AC Input Test Conditions
(0
℃ ≤ TCASE ≤ 85℃ for -18/-25/-3, VDD, VDDQ = 1.8V ± 0.1V)
CONDITION
SYMBOL
VALUE
UNIT
NOTES
Input reference voltage
VREF
0.5 x VDDQ
V
1
Input signal maximum peak to peak swing
VSWING(MAX)
1.0
V
1
Input signal minimum slew rate
SLEW
1.0
V/nS
2, 3
Note:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(ac) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the
range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to
VIL(ac) on the negative transitions
.
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| W9725G6IB-25 | 功能描述:IC DDR2-800 SDRAM 256MB 84-WBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.173"，4.40mm 宽） 供应商设备封装:8-MFP 包装:带卷 (TR) |
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