Datasheet
7
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Contents
Tables
1
Related Documents............................................................................................. 12
2
Intel
LXT384 Transceiver Package Top-Side Markings ....................................16
3
Operating Mode Selections ................................................................................. 19
4
Operating Mode-Specific Signal Names ............................................................. 20
5
Receiver Bipolar/Unipolar I/O Signal Functions .................................................. 21
6
Transmitter Bipolar/Unipolar I/O Signal Functions .............................................. 22
7
Microprocessor-Standard Bus and Interface Signals .......................................... 24
8
Framer/Mapper Receive Signals .........................................................................29
9
Framer/Mapper Transmit Signals........................................................................ 31
10
Line Interface Unit Signals .................................................................................. 34
11
Clocks and Clock-Related Signals ...................................................................... 37
12
Configuration and Mode-Select Signals .............................................................. 39
13
Signal Loss and Line-Code-Violation Signals ..................................................... 41
14
Performance-Monitoring Selections with A3:0 Pins ............................................ 42
15
Power and Grounds ............................................................................................43
16
JTAG Analog Interface Test Signals ................................................................... 44
17
JTAG Digital Interface Test Signals .................................................................... 44
18
Intel
LXT384 Transceiver Line Length Equalizers.............................................45
19
Intel
LXT384 Transceiver Line Length Equalizer Inputs....................................45
20
Line Length Equalizer Inputs............................................................................... 54
21
Component Values to Use with Transformer Circuit ........................................... 59
22
Transmitter Transformer Turns Ratio Selection .................................................. 59
23
Intel
LXT384 Transceiver Operation Mode Summary .......................................70
24
Host Processor Mode - Parallel Interface Selections .......................................... 71
25
Intel
LXT384 Transceiver Register Summary ...................................................75
26
Register Bit Names ............................................................................................. 76
27
Register Addresses for Serial and Parallel Interfaces......................................... 77
28
ID Register, ID - 00h............................................................................................78
29
Analog Loopback Register, ALOOP - 01h...........................................................78
30
Remote Loopback Register, RLOOP - 02h ......................................................... 78
31
TAOS Enable Register, TAOS - 03h ................................................................... 78
32
LOS Status Monitor Register, LOS - 04h ............................................................ 79
33
DFM Status Monitor Register, DFM (05h) for Intel
LXT384 Transceiver ..........79
34
LOS Interrupt Enable Register, LIE - 06h............................................................ 79
35
DFM Interrupt Enable Register, DIE (07h) for Intel
LXT384 Transceiver..........79
36
LOS Interrupt Status Register, LIS - 08h............................................................. 79
37
DFM Interrupt Status Register, DIS (09h) for Intel
LXT384 Transceiver...........79
38
Reset Register, RES - 0Ah.................................................................................. 80
39
Performance-Monitoring Register, MON - 0Bh ................................................... 81
40
Digital Loopback Register, DL - 0Ch ................................................................... 82
41
LOS/AIS Criteria Selection Register, LACS - 0Dh .............................................. 82
42
Automatic TAOS Select Register, ATS - 0Eh...................................................... 82
43
Global Control Register, GCR - 0Fh.................................................................... 83
44
Pulse Shaping Indirect Address Register, PSIAD (10h)...................................... 84
45
Pulse Shaping Data Register, PSDAT (11h) for Intel
LXT384 Transceiver ......84
46
Output Enable Register, OER - 12h .................................................................... 84
47
AIS Status Monitor Register, AIS - 13h ............................................................... 85
48
AIS Interrupt Enable Register, AISIE - 14h ......................................................... 85
49
AIS Interrupt Status Register, AISIS - 15h .......................................................... 85