参数资料
型号: WJLXT384LEB1
厂商: CORTINA SYSTEMS INC
元件分类: 数字传输电路
英文描述: DATACOM, PCM TRANSCEIVER, PQFP144
封装: 20 X 20MM, ROHS COMPLIANT, LQFP-144
文件页数: 70/140页
文件大小: 1514K
代理商: WJLXT384LEB1
35
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
OE
114
E14
DI
Output Driver Enable Input.
Either the (hardware) OE pin or the OER register can be used to
place the transmitter TRING and TTIP outputs immediately into a
high-impedance mode. This supports redundancy applications
without external mechanical relays.
When the LXT384 Transceiver is in the:
Hardware mode and OE is connected:
Low, OE is used to disable all transmit output drivers at one
time, and to place TRING and TTIP outputs into high-
impedance. All other internal circuitry stays active.
High, OE is used to enable transmitter output drivers.
Host Processor mode, instead of the OE pin, you can write a
1 to the OE bit of the OER register to place individual TRING
and TTIP outputs into high-impedance. (See Table 46 in
NOTE: In Host Processor mode, the OE pin when set low
overrides the OER register setting.
RRING7
RRING6
RRING5
RRING4
RRING3
RRING2
RRING1
RRING0
138
133
126
121
66
61
54
49
B7
D7
D8
B8
N8
L8
L7
N7
AI
Receive Ring Input 7:0.
RRING (and RTIP) are differential line receiver inputs (see
The differential signal received at both RRING and RTIP provides
either RDATA, or RPOS/RNEG, depending on mode of operation
(unipolar or bipolar).
NOTE: In clock-recovery mode, the differential signal received at
both RRING and RTIP also provides the recovery clock,
RCLK. For more information on clock recovery, see
RTIP7
RTIP6
RTIP5
RTIP4
RTIP3
RTIP2
RTIP1
RTIP0
139
132
127
120
67
60
55
48
A7
C7
C8
A8
P8
M8
M7
P7
AI
Receive Tip Input 7:0.
For the RTIP description, see RRING (above).
TRING7
TRING6
TRING5
TRING4
TRING3
TRING2
TRING1
TRING0
135
130
123
118
63
58
51
46
A5
C5
C10
A10
P10
M10
M5
P5
AO
Transmit Ring Output 7:0.
TRING (and TTIP) outputs are used to generate a differential
output on the line side of the transmitter transformer.
When the LXT384 Transceiver is in:
Hardware mode, and either OE or TCLK is low, TTIP (and
TRING) are placed in a high-impedance tristate.
Host Processor mode, TRING and TTIP can be placed in a
high-impedance tristate on a port-by-port basis by writing a 1
to the OE bit in the Output Enable Register (OER). OE or
TCLK low also places TTIP/TRING into high-impedance. (For
more information, see Table 46 in Chapter 8.0, “Registers”.)
Table 10. Line Interface Unit Signals (Sheet 2 of 3)
Signal
Name
QFP
Pin
PBGA
Ball
Signal
Type
Signal Description
1. AI: Analog Input. AO: Analog Output. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output.
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