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参数资料
型号： WJLXT384LEB1
厂商： CORTINA SYSTEMS INC
元件分类： 数字传输电路
英文描述： DATACOM, PCM TRANSCEIVER, PQFP144
封装： 20 X 20MM, ROHS COMPLIANT, LQFP-144
文件页数： 59/140页
文件大小： 1514K
代理商： WJLXT384LEB1
25
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
CS / JASEL
87
J11
DI
Chip Select (Active Low) Input.
When the LXT384 Transceiver is in the:
Host Processor mode, CS is used to select a specific
LXT384 Transceiver device so the host processor can
communicate with the registers of that LXT384 Transceiver.
Hardware mode, CS functions as JA Select (JASEL). (See
JASEL in Section 5.6, “Configuration and Mode-Select
Signals”.)
D7 / LOOP7
D6 / LOOP6
D5 / LOOP5
D4 / LOOP4
D3 / LOOP3
D2 / LOOP2
D1 / LOOP1
D0 / LOOP0
28
27
26
25
24
23
22
21
K1
J1
J2
J3
J4
H2
H3
G2
DI/O
(Parallel) Data Bus Input/Output 7:0.
When the LXT384 Transceiver is in the:
Host Processor mode with a parallel interface that is:
Non-multiplexed, D7:0 function as a bi-directional 8-bit
data port.
Multiplexed, D7:0 carry both bi-directional 8-bit data and
the 8 least-significant address lines.
Host processor mode with a serial interface, D7:0 must be
grounded.
Hardware mode, the D7:0 pins function as LOOP7:0. (See
LOOP7:0 in Section 5.4, “Line Interface Unit Signals”.)
DS / SDI / WR/
LEN0
84
J14
DI
Data Strobe (Active Low) Input.
When the LXT384 Transceiver is in the:
Host Processor mode using a Motorola processor, DS acts
as a data strobe.
Hardware mode, DS must be connected to ground.
For other pin functions, see SDI and WR.
INT
82
K13
OD,
DO
Interrupt (Active Low, Open Drain).
INT is an active low, maskable, open drain output. If either an AIS
or LOS interrupt enable bit is enabled, INT goes low to flag the
host processor that the status of LXT384 Transceiver registers
changed state.
The host processor INT input must be set for level triggering.
(For information on the LOS interrupt enable, see Table 34. For
information on the AIS interrupt enable, see Table 48. For
interrupt details, see Section 7.5, “Interrupt Handling”).
INT requires an external 10k
Ω pull-up resistor.
RD / R/W/
LEN1
85
J13
DI
Read Enable (Active Low) Input.
When the LXT384 Transceiver is in the:
Host Processor mode using an Intel processor, RD
functions as a read enable.
Hardware mode, RD must be connected to ground.
For other pin functions, see R/W.
Table 7.
Microprocessor-Standard Bus and Interface Signals (Sheet 2 of 3)
Signal
Name
QFP
Pin
PBGA
Ball
Signal
Type
Signal Description
1. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output. OD: Open Drain
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