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参数资料
型号： WJLXT384LEB1
厂商： CORTINA SYSTEMS INC
元件分类： 数字传输电路
英文描述： DATACOM, PCM TRANSCEIVER, PQFP144
封装： 20 X 20MM, ROHS COMPLIANT, LQFP-144
文件页数： 77/140页
文件大小： 1514K
代理商： WJLXT384LEB1
41
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
5.7
Signal Loss and Line-Code-Violation Signals
Table 13 lists and the signal loss and line-code violation signals for the LXT384 Transceiver.
Table 13. Signal Loss and Line-Code-Violation Signals
Signal
Name
QFP
Pin
PBGA
Ball
I/O1
Signal Description
A4
A3
A2
A1
A0
12
13
14
15
16
F4
F3
F2
F1
G3
DI
Performance Monitoring Input.
When the LXT384 Transceiver is in the:
Hardware mode, the A3:0 pins make the performance-
monitoring selections shown in Table 14. A4 must be connected
to ground.
Host Processor mode:
These pins no longer control the monitoring function. Instead,
in non-multiplexed host mode, these pins function as non-
multiplexed address pins (see Section 5.2, “Microprocessor-
Standard Bus and Interface Signals”).
For information on how to control performance monitoring,
see Table 39, “Performance-Monitoring Register, MON - 0Bh”
on page 81.
BPV7:0
Bipolar Violation Detect Output 7:0.
For information on the BPV signals, see Section 5.3, “Framer/
Mapper Signals”.
CLKE
Clock Edge Select Input.
For information on how CLKE is used for clock and data recovery,
see Section 5.5, “Clocks and Clock-Related Signals”.
LOS7
LOS6
LOS5
LOS4
LOS3
LOS2
LOS1
LOS0
140
3
106
113
68
75
35
42
E4
E3
E12
E11
K11
K12
K3
K4
DO
Loss of Signal Output.
LOS is:
Low when a loss-of-signal condition is cleared (incoming signal
with normal levels, being processed through the transceiver).
High (indicating a loss of signal), when there is no incoming
signal (sequence of marks for a specified time interval).
NOTE: When a loss-of-signal condition is cleared, LOS returns to
low when an incoming signal has a sufficient number of
transitions in a specified time interval. (For details, see
Section 6.3.3, “Receiver Loss-Of-Signal Detector”.)
RCLK7:0
Receive Clock Output 7:0.
For information on how RCLK is used for clock and data recovery,
see Section 5.3, “Framer/Mapper Signals”.
1. DI: Digital Input. DO: Digital Output.
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