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参数资料
型号： WJLXT384LEB1
厂商： CORTINA SYSTEMS INC
元件分类： 数字传输电路
英文描述： DATACOM, PCM TRANSCEIVER, PQFP144
封装： 20 X 20MM, ROHS COMPLIANT, LQFP-144
文件页数： 58/140页
文件大小： 1514K
代理商： WJLXT384LEB1
24
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
5.2
Microprocessor-Standard Bus and Interface Signals
Table 7 lists and describes the microprocessor-standard bus and interface signals for the LXT384
Transceiver.
For multi-function pins, the pin name in blue bold print indicates the signal being discussed.
Note:
For information on selecting parallel or serial interfaces, see the signal description for MODE in
Section 5.6, “Configuration and Mode-Select Signals”, Table 12.
Table 7.
Microprocessor-Standard Bus and Interface Signals (Sheet 1 of 3)
Signal
Name
QFP
Pin
PBGA
Ball
Signal
Type
Signal Description
A4
A3
A2
A1
A0
12
13
14
15
16
F4
F3
F2
F1
G3
DI
Address Select Input 4:0.
When the LXT384 Transceiver is in the:
Host Processor mode using a parallel interface that is in the:
Non-multiplexed mode, A4:0 function as address pins.
Multiplexed mode, A4:0 must be connected to multiplexed
Address/Data Bus (AD).
Hardware mode, must be connected to ground. See Section
5.7, “Signal Loss and Line-Code-Violation Signals” for other
pin functions.
ACK / RDY /
SDO
83
K14
DO
Data Transfer Acknowledge (Active Low) Output.
When the LXT384 Transceiver is in the Host Processor mode
using a Motorola processor, ACK acts as a data transfer
acknowledge. A low signal on ACK during a data bus operation
that is a:
Read operation indicates valid data.
Write operation is an acknowledge signal that indicates a
data transfer into an addressed register is accepted.
NOTE: Wait states occur only if a write cycle immediately follows
a previous read or write cycle (for example, read-modify-
write).
For other pin functions, see RDY and SDO.
ALE / AS /
SCLK/LEN2
86
J12
DI
Address Latch Enable Input.
When the LXT384 Transceiver is in the:
Host Processor mode using an Intel
processor in a parallel
interface, ALE acts as an address latch enable. In this case,
the address on the multiplexed address/data bus pins D7:0
(also called AD7:0) is clocked into the LXT384 Transceiver
with the falling edge of ALE.
Hardware mode, ALE must be connected to ground.
For other pin functions, see AS and SCLK.
ALE / AS /
SCLK/LEN2
86
J12
DI
Address Strobe (Active Low) Input.
When the LXT384 Transceiver is in the:
Host Processor mode using a Motorola processor in a
parallel interface, AS acts as an active-low address strobe.
Hardware mode, AS must be connected to ground.
For other pin functions, see ALE and SCLK.
1. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output. OD: Open Drain
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