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参数资料
型号： WJLXT384LEB1
厂商： CORTINA SYSTEMS INC
元件分类： 数字传输电路
英文描述： DATACOM, PCM TRANSCEIVER, PQFP144
封装： 20 X 20MM, ROHS COMPLIANT, LQFP-144
文件页数： 65/140页
文件大小： 1514K
代理商： WJLXT384LEB1
30
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
BPV7 / RNEG7
BPV6 / RNEG6
BPV5 / RNEG5
BPV4 / RNEG4
BPV3 / RNEG3
BPV2 / RNEG2
BPV1 / RNEG1
BPV0 / RNEG0
141
4
105
112
69
76
34
41
A3
C3
C12
A12
P12
M12
M3
P3
DO
Receive Negative Data Output 7:0.
This signal description applies to both RNEG and RPOS in
bipolar I/O mode. When the LXT384 Transceiver is in the:
Host processor mode, during an LOS condition, AIS
can be inserted into the receive path. See the
description of the GCR register RAISEN bit, in Section
6.3.6, “Receive Alarm Indication Signal (RAIS) Enable”
on page 50.
Hardware mode, RNEG and RPOS remain active
during an LOS condition.
When MCLK is provided with a clocking signal:
The LXT384 Transceiver enters clock-recovery mode.
RNEG[7:0] act as active-high bipolar Non Return to
Zero (NRZ) receive signal outputs.
A High signal on RNEG corresponds to receipt of a
negative pulse on RTIP/RRING.
A High signal on RPOS corresponds to receipt of a
positive pulse on RTIP/RRING.
These signals are valid on the falling or rising edges of
RCLK, depending on the CLKE input. See the CLKE
pin description in Table 11, “Clocks and Clock-Related
Signals” on page 37.
When MCLK is high:
The LXT384 Transceiver enters data recovery mode.
RNEG[7:0] act as RZ data receiver outputs.
These signals are valid on the falling or rising edges of
RCLK, depending on the CLKE input. See the CLKE
pin description in Table 11, “Clocks and Clock-Related
Signals” on page 37.
When MCLK is low:
RNEG and RPOS can be placed in a high-impedance
tristate with the MCLK pin. (For details, see MCLK in
Section 5.5, “Clocks and Clock-Related Signals”.)
NOTE: For pin functions involving unipolar mode, see the
BPV pin description.
RDATA7 / RPOS7
RDATA6 / RPOS6
RDATA5 / RPOS5
RDATA4 / RPOS4
RDATA3 / RPOS3
RDATA2 / RPOS2
RDATA1 / RPOS1
RDATA0 / RPOS0
142
5
104
111
70
77
33
40
A2
C2
C13
A13
P13
M13
M2
P2
DO
Receive Positive Data Output 7:0.
For the RPOS description, see RNEG.
NOTE: For pin functions involving unipolar mode, see the
RDATA pin description.
Table 8.
Framer/Mapper Receive Signals (Sheet 2 of 2)
Signal
Name
QFP
Pin
PBGA
Ball
Signal
Type
Signal Description
1. AI: Analog Input. AO: Analog Output. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output.
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