Datasheet
5
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Contents
12.0
Line-Interface-Unit Circuit Specifications....................................................123
13.0
Mask Specifications ..............................................................................................124
14.0
Jitter Performance .................................................................................................126
15.0
Recommendations and Specifications .........................................................131
16.0
Mechanical Specifications..................................................................................133
16.1
Top Label Markings........................................................................................... 135
17.0
Product Ordering Information...........................................................................137
18.0
Package Information.............................................................................................138
19.0
Abbreviations and Acronyms ...........................................................................139
Figures
1
Intel LXT384 Transceiver High-Level Block Diagram ........................................14
2
Intel LXT384 Transceiver Detailed Block Diagram............................................ 15
3
Intel LXT384 Transceiver 144-Pin Assignments ...............................................17
4
Intel LXT384 Transceiver Plastic Ball Grid Array (PBGA) Pin Assignments ..... 18
5
50% AMI Encoding.............................................................................................. 53
6
Intel LXT384 Transceiver External Transmit/Receive Line Circuitry ................. 58
7
Jitter Attenuator ................................................................................................... 60
8
Intel LXT384 Transceiver Analog Loopback ..................................................... 62
9
Intel LXT384 Transceiver Digital Loopback....................................................... 63
10
Intel LXT384 Transceiver Remote Loopback ....................................................64
11
TAOS Data Path for Intel LXT384 Transceiver ................................................. 65
12
TAOS with Analog Loopback for Intel LXT384 Transceiver .............................. 66
13
TAOS with Digital Loopback for Intel LXT384 Transceiver ............................... 66
14
Host Processor Mode - Serial Interface Read Timing ......................................... 73
15
JTAG Architecture ............................................................................................... 86
16
JTAG State Diagram ........................................................................................... 88
17
Analog Test Port Application ............................................................................... 93
18
JTAG Timing ....................................................................................................... 95
19
Intel LXT384 Transceiver - Transmit Timing ................................................... 106
20
Intel LXT384 Transceiver - Receive Timing .................................................... 108
21
Intel Processor Non-Multiplexed Interface - Read Timing ...............................110
22
Intel Processor Multiplexed Interface - Read Timing....................................... 111
23
Intel Processor Non-Multiplexed Interface - Write Timing ...............................113
24
Intel Processor Multiplexed Interface - Write Timing ....................................... 114
25
Motorola Processor Non-Multiplexed Interface - Read Timing.......................... 116
26
Motorola Processor Multiplexed Interface - Read Timing ................................. 117
27
Motorola Processor Non-Multiplexed Interface - Write Timing.......................... 119
28
Motorola Processor Multiplexed Interface - Write Timing.................................. 120
29
Serial Input Timing ............................................................................................ 121
30
Serial Output Timing..........................................................................................122
31
E1, ITU G.703 Mask Template .......................................................................... 124
32
T1, T1.102 Mask Templates for LXT384........................................................... 125
33
Intel LXT384 Transceiver Jitter Tolerance Performance................................. 128
34
Intel LXT384 Transceiver Jitter Transfer Performance ................................... 129