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参数资料
型号： WJLXT384LEB1
厂商： CORTINA SYSTEMS INC
元件分类： 数字传输电路
英文描述： DATACOM, PCM TRANSCEIVER, PQFP144
封装： 20 X 20MM, ROHS COMPLIANT, LQFP-144
文件页数： 94/140页
文件大小： 1514K
代理商： WJLXT384LEB1
57
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
6.5
Line-Interface Protection
Figure 6 shows circuitry for line-interface protection. (While not mandatory for normal operation,
Intel
strongly recommends these line-interface protection elements.) For the appropriate values
and tolerances of devices used with line-interface protection circuitry, see Table 73 in Chapter 12.0,
“Line-Interface-Unit Circuit Specifications”.
Receive side. Two 1k
Ω resistors protect the receiver against current surges that can couple
into the LXT384 Transceiver. Due to the high receiver impedance (typically 70 k
Ω), these
resistors do not affect the receiver sensitivity.
Transmit side. Resistors RT and Schottky diodes D1-4 protect the output drivers from line
surges. To protect the LXT384 Transceiver output driver from surge currents in excess of 100
mA, a transient voltage suppressor TVS1 (such as Teccor P0080S) is required.
For some power-up operations, on rare occasions there is no activity for several seconds on all of
the following transmit-side pins: TPOS, TNEG, TCLK, and MCLK. If this lack of activity occurs
for a period of several seconds, then it can cause transmitter outputs to remain in their last-known
logic state. If the transmitter outputs are in static mode. As a result, then the transformer output
appears as a short circuit to this static DC voltage.
In the worst case of inactivity, one of the transmitter outputs is high while other transmitter outputs
are low. In this case, outputs TTIP and TRING would draw excessive current through the
transformer primary windings and the LXT384 Transceiver can overheat. To manage this type of
power-up operation, do only one of the following:
Set OE low until normal operations return.
Set TCLK low until normal operations return.
Set TNEG low until normal operations return.
Set TPOS low until normal operations return.
Provide MCLK with a frequency from 10 kHz to 10 MHz until normal operations return.
Provide TCLK with a frequency from 100 kHz to 10 MHz until normal operations return.
Toggle TNEG with a clock from 100 kHz to 10 MHz until normal operations return.
Toggle TPOS with a clock from 100 kHz to 10 MHz until normal operations return.
As shown in Figure 6, add a single 0.47 uF capacitor in series with one of the RT output
resistors.
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