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参数资料
型号： WJLXT384LEB1
厂商： CORTINA SYSTEMS INC
元件分类： 数字传输电路
英文描述： DATACOM, PCM TRANSCEIVER, PQFP144
封装： 20 X 20MM, ROHS COMPLIANT, LQFP-144
文件页数： 80/140页
文件大小： 1514K
代理商： WJLXT384LEB1
44
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
5.9
Test Signals
Table 17 lists and describes the LXT384 Transceiver test signals, which are used to test all digital
input, output, and input/output pins.
The JTAG test signals are compatible with the IEEE 1149.1 boundary-scan test.
Table 16. JTAG Analog Interface Test Signals
Signal
Name
QFP
Pin
PBGA
Ball
Signal
Type
Signal Description
AT2
AT1
93
94
G13
H13
AO
AI
JTAG Analog Test Port 2:1.
AT2 is the JTAG analog output test port.
AT1 is the JTAG analog input test port.
Both test ports are used for test purposes.
See Section 9.4.2, “Analog Port Scan Register (ASR)” on page 94
and Figure 17, “Analog Test Port Application” on page 93.
1. AI: Analog Input. AO: Analog Output.
Table 17. JTAG Digital Interface Test Signals
Signal
Name
QFP
Pin
PBGA
Ball
Signal
Type
Signal Description
TCK
97
F14
DI
JTAG Test Clock Input.
TCK is the clock input for JTAG.
When TCK is not used, connect it to ground.
TDI
99
F12
DI
JTAG Test Data Input.
TDI, the test data input for JTAG, is used for loading serial
instructions and data into internal test logic. TDI is sampled on the
rising edge of TCK.
TDI is connected high internally and can be left disconnected.
TDO
98
F13
DO
JTAG Test Data Output.
TDO, the test data output for JTAG, is used for reading all serial
configuration and test data from the internal LXT384 Transceiver
test logic. It is updated on the falling edge of TCK.
TMS
96
F11
DI
JTAG Test Mode Select Input.
TMS, used to control the test-logic state machine, is sampled on
the rising edge of TCK.
TMS is connected high internally and can be left disconnected.
TRST
95
G12
DI
JTAG Controller Reset Input.
TRST is used to reset the JTAG controller.
TRST is connected high internally and can be left disconnected.
1. DI: Digital Input. DO: Digital Output.
2. See Section 9.4.5, “Instruction Register (IR)” on page 95. Figure 15, “JTAG Architecture” on page 86. and
Figure 18, “JTAG Timing” on page 95.
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