- 您现在的位置：买卖IC网 > PDF目录68583 > WJLXT384LEB1 (CORTINA SYSTEMS INC) DATACOM, PCM TRANSCEIVER, PQFP144 PDF资料下载
参数资料
| 型号： | WJLXT384LEB1 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PQFP144 |
| 封装： | 20 X 20MM, ROHS COMPLIANT, LQFP-144 |
| 文件页数： | 61/140页 |
| 文件大小： | 1514K |
| 代理商： | WJLXT384LEB1 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页当前第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页
27
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
5.3
Framer/Mapper Signals
Framer/mapper signals are used to interface the LXT384 Transceiver to a framer/mapper.
5.3.1
Bipolar vs. Unipolar Operation - Receive Side
Table 5 on page 21 lists receive-side framer/mapper signals, which can connect to a framer/mapper
using either bipolar or unipolar interface connections. Table 8 lists details.
Depending on the state of a UBS7:0 pin, both the corresponding receiver and transmitter pins are
automatically set for either bipolar I/O or unipolar I/O. When a UBS pin is connected:
Low, bipolar I/O is selected.
High for more than 16 consecutive MCLK clock cycles, unipolar I/O is selected.
Receive side - Bipolar I/O. When TNEG/UBS is connected low, then bipolar I/O is selected and
RNEG/RPOS functions are selected. In this case, the signal flow occurs as follows:
1. The receiver routes receive analog signals from RTIP/RRING to a data recovery circuit.
2. The data recovery circuit converts the incoming line AMI signals, which consist of positive
and negative pulses, into a sequence of logic zeroes and ones. It then outputs the resulting
information onto RNEG and RPOS.
3. The recovered clock from RTIP/RRING is output at RCLK.
4. The RNEG and RPOS data lines and the RCLK clock line connect the LXT384 Transceiver to
a framer/mapper. A logic ‘1’ on:
— RNEG indicates that a negative pulse is detected on the line, and corresponds to the
receipt of a negative pulse on RRING/RTIP.
— RPOS indicates that a positive pulse is detected on the line, and corresponds to the receipt
of a positive pulse on RRING/RTIP.
— The receiver outputs the recovered clock at RCLK. RCLK synchronizes the data transfer
into the framer/mapper.
5. RNEG/RPOS validation relative to RCLK is selectable with CLKE pin polarity. See the CLKE
pin description in Table 11, “Clocks and Clock-Related Signals” on page 37.
Note:
In bipolar I/O mode, the framer/mapper is responsible for detecting any line-code violations that
appear on the line. The framer/mapper also decodes HDB3.
Receive side - Unipolar I/O. When TNEG/UBS is connected high for more than 16 consecutive
MCLK cycles, then unipolar I/O is selected and RDATA/BPV functions are active. RDATA does
not distinguish between a positive or a negative pulse on the line. In this case, the signal flow
occurs as follows:
1. RDATA and RCLK connect the LXT384 Transceiver to a framer/mapper, while BPV acts as a
bipolar violation detector. The LXT384 Transceiver internally decodes HDB3/AMI.
2. The receiver outputs the recovered clock at RCLK. RCLK synchronizes the data transfer into
the framer/mapper.
3. RDATA does not include information about the polarity of the marks at RTIP/RRING.
4. RDATA validation relative to RCLK is selectable with CLKE pin polarity. See the CLKE pin
description in Table 11, “Clocks and Clock-Related Signals” on page 37.
相关PDF资料 |
PDF描述 |
|---|---|
| WJLXT385LEB1 | DATACOM, PCM TRANSCEIVER, PQFP144 |
| WJLXT385LEB1 | DATACOM, PCM TRANSCEIVER, PQFP144 |
| WJLXT386LEB2 | DATACOM, PCM TRANSCEIVER, PQFP100 |
| WJLXT386LEB2 | DATACOM, PCM TRANSCEIVER, PQFP100 |
| WJLXT388LEB2 | DATACOM, PCM TRANSCEIVER, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| WJLXT386LE.B2 | 功能描述:IC TRANS QUAD T1/E1/J1 100-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
| WJLXT6155LE.B5 | 制造商:Intel 功能描述:SONET/SDH/ATM Transceiver 1TX 1RX 64-Pin LQFP |
| WJLXT6155LE.B5-866255 | 功能描述:TXRX SDH/SONET/ATM HS 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:收发器 驱动器/接收器数:1/1 规程:RS422，RS485 电源电压:4.75 V ~ 5.25 V 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 产品目录页面:1402 (CN2011-ZH PDF) |
| WJLXT6155LE.B5-866256 | 制造商:Cortina Systems Inc 功能描述:SONET/SDH/ATM Transceiver 1TX 1RX 64-Pin LQFP T/R |
| WJLXT901ALC.A4 | 功能描述:IC 10BASE-T/AUI TXCVR 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
发布紧急采购，3分钟左右您将得到回复。