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参数资料
型号： WJLXT384LEB1
厂商： CORTINA SYSTEMS INC
元件分类： 数字传输电路
英文描述： DATACOM, PCM TRANSCEIVER, PQFP144
封装： 20 X 20MM, ROHS COMPLIANT, LQFP-144
文件页数： 63/140页
文件大小： 1514K
代理商： WJLXT384LEB1
29
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
5.3.3
Framer/Mapper Signals - Details
Table 8 lists and describes the LXT384 Transceiver framer/mapper receive signals.
Table 9 on page 31 lists and describes the LXT384 Transceiver framer/mapper transmit
signals.
For multi-function pins, the pin name in blue bold print indicates the signal being discussed.
Table 8.
Framer/Mapper Receive Signals (Sheet 1 of 2)
Signal
Name
QFP
Pin
PBGA
Ball
Signal
Type
Signal Description
BPV7 / RNEG7
BPV6 / RNEG6
BPV5 / RNEG5
BPV4 / RNEG4
BPV3 / RNEG3
BPV2 / RNEG2
BPV1 / RNEG1
BPV0 / RNEG0
141
4
105
112
69
76
34
41
A3
C3
C12
A12
P12
M12
M3
P3
DO
Bipolar Violation Detect Output 7:0.
When unipolar I/O is selected for the LXT384 Transceiver,
BPV acts as an output line code violation detector. If the
LXT384 Transceiver:
Does not detect an in-service line code violation, BPV
remains low.
Detects an in-service line code violation, it asserts BPV
high.
For details on Line Code Violations, see Section 5.7, “Signal
Loss and Line-Code-Violation Signals”.
For other pin functions, see RNEG.
RCLK7
RCLK6
RCLK5
RCLK4
RCLK3
RCLK2
RCLK1
RCLK0
143
6
103
110
71
78
32
39
A1
C1
C14
A14
P14
M14
M1
P1
DO
Receive Clock Output 7:0.
Normally, this pin provides the recovered clock from the
signal received at RTIP and RRING. Under LOS conditions,
MCLK replaces RCLK at the RCLK output. For details, see
Section 6.3.3, “Receiver Loss-Of-Signal Detector”.
When MCLK is Low:
The LXT384 Transceiver enters the data recovery
mode.
RCLK will be in high impedance state.
When MCLK is High:
The clock recovery circuit is disabled.
The RCLK output is then the EX-OR of RPOS and
RNEG. This produces a pseudo-recovered clock.
For details about the relationship between MCLK and
RCLK, see Section 5.5, “Clocks and Clock-Related
Signals”, especially Table 11 on page 37.
RDATA7 / RPOS7
RDATA6 / RPOS6
RDATA5 / RPOS5
RDATA4 / RPOS4
RDATA3 / RPOS3
RDATA2 / RPOS2
RDATA1 / RPOS1
RDATA0 / RPOS0
142
5
104
111
70
77
33
40
A2
C2
C13
A13
P13
M13
M2
P2
DO
Receive Data Output 7:0.
When unipolar I/O is selected for the LXT384 Transceiver,
RDATA acts as the receive data output.
See Section 5.3.1, “Bipolar vs. Unipolar Operation - Receive
Side” on page 27.
For other pin functions, see RPOS.
1. AI: Analog Input. AO: Analog Output. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output.
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