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参数资料
型号： WJLXT384LEB1
厂商： CORTINA SYSTEMS INC
元件分类： 数字传输电路
英文描述： DATACOM, PCM TRANSCEIVER, PQFP144
封装： 20 X 20MM, ROHS COMPLIANT, LQFP-144
文件页数： 66/140页
文件大小： 1514K
代理商： WJLXT384LEB1
31
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Table 9.
Framer/Mapper Transmit Signals (Sheet 1 of 3)
Signal
Name
QFP
Pin
PBGA
Ball
Signal
Type
Signal Description
TCLK7
TCLK6
TCLK5
TCLK4
TCLK3
TCLK2
TCLK1
TCLK0
2
9
100
107
74
81
29
36
B1
D1
D14
B14
N14
L14
L1
N1
DI
Transmit Clock Input 7:0.
When the LXT384 Transceiver is in Hardware mode and
TCLK is:
Operating with a normal clock signal, TPOS and TNEG
are sampled on the falling edge of TCLK.
Low and remains in a low state, the transmitter output
drivers enter a low-power high-impedance tristate.
High (for more than 16 consecutive MCLK clock
cycles), and MCLK is:
operating normally as a clock, the LXT384
Transceiver enters the TAOS mode. (For details, see
Section 6.8, “Transmit All Ones Operations”.
not operating as a clock, but is either low or high, the
pulse-shaper circuit shown in Figure 1 is disabled.
For information on how to prevent damage to the
LXT384 Transceiver when pulse shaping is disabled,
see Section 6.4.2, “Transmitter Pulse Shaping”.)
)
NOTE: When the LXT384 Transceiver is in the Host
Processor mode, TAOS mode can be selected
using registers in Chapter 8.0, “Registers”.
When pulse shaping is disabled, it is possible to overheat
and damage the LXT384 Transceiver by leaving transmit
inputs high continuously. For example a programmable
ASIC might leave all outputs high over an extended period,
until it is programmed. To prevent this, clock one of these
signals: TPOS, TNEG, TCLK, or MCLK. Another solution is
to set one of these signals low: TPOS, TNEG, TCLK, or OE.
Note: The TAOS generator uses MCLK as a timing
reference. In order to assure that the output
frequency is within specification limits, MCLK must
have the applicable stability.
TCLK
MCLK
Result
Normal Clock
Don’t
care
TNEG and TPOS
sampled on falling
edge of TCLK
Low
Don’t
care
Transmitter driver
outputs enter high-
impedance tristate
High for 16
consecutive
MCLK cycles
Either
high or
low
Disables transmit
pulse shaping
High for 16
consecutive
MCLK cycles
Normal
Clock
TAOS
相关PDF资料
PDF描述
WJLXT385LEB1 DATACOM, PCM TRANSCEIVER, PQFP144
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