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参数资料
型号： WJLXT384LEB1
厂商： CORTINA SYSTEMS INC
元件分类： 数字传输电路
英文描述： DATACOM, PCM TRANSCEIVER, PQFP144
封装： 20 X 20MM, ROHS COMPLIANT, LQFP-144
文件页数： 118/140页
文件大小： 1514K
代理商： WJLXT384LEB1
79
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Table 32. LOS Status Monitor Register, LOS - 04h
Bit
Name
Description
R/W
7:0
LOS7:0
Loss Of Signal Status Monitor.
On power-up, the LOS7:0 bits are cleared to ‘0’.
All LOS interrupts are cleared by a single read operation.
Each time the LOS detector detects a valid loss-of-signal condition on a
receiver, its corresponding LOS bit is set to ‘1’.
R
Table 33. DFM Status Monitor Register, DFM (05h) for Intel LXT384 Transceiver
Bit
Name
Function1
7-0
DFM7-DFM0
Respective bit(s) are set to “1” every time the short circuit monitor detects a valid
secondary output driver short circuit condition in transceivers 7-0. Note: DFM is
available only in configurations with no transmit series resistors (T1 mode with
TVCC=3.3V).
1. On power-up all the register bits are set to “0”. All DFM interrupts are cleared by a single read operation.
Table 34. LOS Interrupt Enable Register, LIE - 06h
Bit
Name
Description
R/W
7:0
LIE7:0
Loss Of Signal Interrupt Enable.
On power-up, the LIE7:0 bits are cleared to ‘0’ and all LOS interrupts are
disabled.
Writing a ‘1’ to an LIE bit enables an LOS interrupt for its corresponding
receiver.
R/W
Table 35. DFM Interrupt Enable Register, DIE (07h) for Intel
LXT384 Transceiver
Bit
Name
Function
1
7-0
DIE7-DIE0
Transceiver 7-0 DFM interrupts are enabled by writing a “1” to the respective bit.
1. On power-up all the register bits are set to “0” and all interrupts are disabled.
Table 36. LOS Interrupt Status Register, LIS - 08h
Bit
Name
Description
R/W
7:0
LIS7:0
Loss Of Signal Interrupt Status.
On power-up, the LIS7:0 bits are cleared to ‘0’.
After an LOS interrupt is cleared, then each time there is a change in the
LOS status of a receiver, the corresponding LIS bit is set to ‘1’.
R
Table 37. DFM Interrupt Status Register, DIS (09h) for Intel
LXT384 Transceiver
Bit
Name
Function1
7-0
DIS7-DIS0
These bits are set to “1” every time a DFM status change has occurred since the last
cleared interrupt in transceivers 7-0 respectively.
1. On power up all register bits are set to “0”.
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