参数资料
型号: WJLXT384LEB1
厂商: CORTINA SYSTEMS INC
元件分类: 数字传输电路
英文描述: DATACOM, PCM TRANSCEIVER, PQFP144
封装: 20 X 20MM, ROHS COMPLIANT, LQFP-144
文件页数: 12/140页
文件大小: 1514K
代理商: WJLXT384LEB1
109
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
11.2
Host Processor Mode - Parallel Interface Timing
This sections gives timing characteristics and timing diagrams for both Intel
processors and
Motorola processors.
11.2.1
Intel Processor - Parallel Interface Timing
Table 67 lists read timing characteristics for the Intel
processor.
Table 67. Intel Processor - Read Timing Characteristics
Parameter
Sym.
Min.1
Max.1
Unit
Test
Conditions
Address setup time to latch
tSALR
10
ns
CLoad = 100
pF on D7:0.
All other
outputs are
loaded with
50 pF.
Valid address latch pulse width
tVL
30
ns
Latch active to active read setup time
tSLR
10
ns
Chip select setup time to active read
tSCSR
0–
ns
Chip select hold time from inactive read
tHSCR
0–
ns
Address hold time from inactive ALE
tHALR
5ns
Active read to data valid delay time
tPRD
10
50
ns
Address setup time to RD inactive
tHAR
1–
ns
Address hold time from RD inactive
tSAR
5–
ns
Inactive read to data high-impedance tristate delay
time
tZRD
335
ns
Valid read signal pulse width
tVRD
60
ns
Inactive read to inactive INT delay time
tINT
–10
ns
Active chip select to RDY delay time
tDRDY
012
ns
Active ready low time
tVRDY
–40
ns
Inactive ready to high-impedance tristate delay time
tRDYZ
–3
ns
1. Minimum and maximum values are at 25 C° and are for design aid only, not guaranteed, and not subject
to production testing.
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