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| 型号： | WJLXT384LEB1 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PQFP144 |
| 封装： | 20 X 20MM, ROHS COMPLIANT, LQFP-144 |
| 文件页数： | 83/140页 |
| 文件大小： | 1514K |
| 代理商： | WJLXT384LEB1 |
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47
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
6.1
Functional Overview
The LXT384 Transceiver is a fully integrated octal line interface unit designed for T1 1.544 Mbps
and 2.048 Mbps (E1) short-haul applications. (For a block diagram, see Figure 1.)
The LXT384 Transceiver can be controlled either by a ‘Hardware mode’ that uses hard-wired pins
or by a ‘Host Processor mode’, which uses either a serial or parallel host processor interface that is
controlled in software. (For more information on selecting an operating mode, see Table 3 in
Each transceiver front end interfaces with four lines: one pair of two lines for transmit, and one pair
of two lines for receive. These two pairs make up a digital data loop for full-duplex transmission.
The TCLK pin provides the transmitter timing reference, and the MCLK pin provides the receiver
reference clock. The LXT384 Transceiver is designed to operate without any reference clock when
it is used as an analog front end (that is, for data recovery in the receiver path and as a line driver in
the transmit path). MCLK is mandatory if on-chip clock recovery is required.
Note:
MCLK should be true to the recovered clock of the incoming data. It should be only
plesiochronous to MCLK.
All eight clock-recovery circuits share the same reference clock defined by the MCLK input signal.
(For details on MCLK, see Table 11 in Section 5.5, “Clocks and Clock-Related Signals”.)
6.2
Initialization and Reset
Initialization for the LXT384 Transceiver occurs as follows:
1. During power-up, the LXT384 Transceiver is in an unknown state until the power supply
reaches approximately 60% of VCC. Also during power-up, an initial reset sets all registers to
their default values and resets the status and state machines for the LOS detector circuit.
(Between 50 and 70% of VCC, the LXT384 Transceiver is in a critical zone. For more
information about this critical zone, see the application note on slow power-up rise time,
referenced in Section 1.3, “Related Documents”.)
2. A write to the reset register (RES, Table 38) initiates a reset cycle that results in setting all
LXT384 Transceiver registers to their default values. When the reset cycle occurs:
a. In the Intel processor non-multiplexed mode, the reset cycle is 2 microseconds long.
b. In all other modes, the reset cycle is 1 microsecond long.
Note:
For more information related to reset, see Section 7.4.1, “Host Processor Mode - Parallel
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