参数资料
型号: WJLXT384LEB1
厂商: CORTINA SYSTEMS INC
元件分类: 数字传输电路
英文描述: DATACOM, PCM TRANSCEIVER, PQFP144
封装: 20 X 20MM, ROHS COMPLIANT, LQFP-144
文件页数: 127/140页
文件大小: 1514K
代理商: WJLXT384LEB1
87
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
9.3
TAP Controller
The TAP controller is a 16-state synchronous state machine controlled by the TMS input and
clocked by TCK (see Figure 16).The TAP controls whether the LXT384 Transceiver is in reset
mode, receiving an instruction, receiving data, transmitting data or in an idle state. Table 50
describes in detail each of the states represented in Figure 16.
Table 50. TAP State Description
State
Description
Test Logic Reset
In this state the test logic is disabled. The device is set to normal operation mode. While in
this state, the instruction register is set to the ICODE instruction.
Run -Test / Idle
The TAP controller stays in this state as long as TMS is Low. Used to perform tests.
Capture - DR
The Boundary Scan Data Register (BSR) is loaded with input pin data.
Shift - DR
Shifts the selected test data registers by one stage toward its serial output.
Update - DR
Data is latched into the parallel output of the BSR when selected.
Capture - IR
Used to load the instruction register with a fixed instruction.
Shift - IR
Shifts the instruction register by one stage.
Update - IR
Loads a new instruction into the instruction register.
Pause - IR
Pause - DR
Momentarily pauses shifting of data through the data/instruction registers.
Exit1 - IR
Exit1 - DR
Exit2 - IR
Exit2 - DR
Temporary states that can be used to terminate the scanning process.
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