Intel
82865G/82865GV GMCH Datasheet
101
Register Description
3.7
Integrated Graphics Device Registers (Device 2)
Function 0 can be VGA compatible or not; this is selected through GC[bit 1] (offset 52, Device 0).
This section contains the Integrated Graphics Device PCI configuration registers listed in order of
ascending offset address. The register address map is shown in
Table 10
.
Table 10. Integrated Graphics Device PCI Register Address Map (Device 2)
Address
Offset
Register
Symbol
Register Name
Default Value
Access
00–01h
VID2
Vendor Identification
8086h
RO
02–03h
DID2
Device Identification
2572h
RO
04–05h
PCICMD2
PCI Command
0000h
RO,R/W
06–07h
PCISTS2
PCI Status
0090h
RO,R/WC
08h
RID2
Revision Identification
See register
description
RO
09–0Bh
CC
Class Code
030000h
RO
0Ch
CLS
Cache Line Size
00h
RO
0Dh
MLT2
Master Latency Timer
00h
RO
0Eh
HDR2
Header Type
00h
RO
0Fh
—
Intel Reserved
—
—
10–13h
GMADR
Graphics Memory Range Address
00000008h
R/W,RO
14–17h
MMADR
Memory-Mapped Range Address
00000000h
R/W,RO
18–1Bh
IOBAR
IO Decode
00000000h
R/W
1C–2Bh
—
Reserved
—
—
2C–2Dh
SVID2
Subsystem Vendor Identification
0000h
R/WO
2E–2Fh
SID2
Subsystem Identification
0000h
R/WO
30–33h
ROMADR
Video BIOS ROM Base Address
00000000h
RO
34h
CAPPOINT
Capabilities Pointer
D0h
RO
35–3Bh
—
Reserved
—
—
3Ch
INTRLINE
Interrupt Line
00h
R/W, RO
3Dh
INTRPIN
Interrupt Pin
01h
RO
3Eh
MINGNT
Minimum Grant
00h
RO
3Fh
MAXLAT
Maximum Latency
00h
RO
40–CFh
—
Intel Reserved
00h
—
D0–D1h
PMCAPID
Power Management Capabilities ID
0001h
RO
D2–D3h
PMCAP
Power Management Capabilities
0021h
RO
D4–D5h
PMCS
Power Management Control
0000h
R/W,RO
D6–DFh
—
Intel Reserved
—
—
E0–E1h
SWSMI
Software SMI Interface
0000h
R/W
E2–FFh
—
Intel Reserved
—
—