Intel
82865G/82865GV GMCH Datasheet
145
System Address Map
PCI Memory Address Range (Top of Main Memory to 4 GB)
The address range from the top of main SDRAM to 4 GB (top of physical memory space supported
by the GMCH) is normally mapped via the hub interface to PCI.
As a memory controller hub, there is one exception to this rule.
Addresses decoded to MMIO for DRAM RCOMP configuration registers.
As an internal graphics configuration, there are two exceptions to this rule. Both of these exception
cases are forwarded to the IGD.
Addresses decoded to graphics configuration registers.
Addresses decoded to the memory-mapped range of the Internal Graphics Device (IGD).
As an AGP configuration, there are two exceptions to this rule.
Addresses decoded to the AGP memory window defined by the MBASE, MLIMIT, PMBASE,
and PMLIMIT registers are mapped to AGP.
Addresses decoded to the graphics aperture range defined by the APBASE and APSIZE
registers are mapped to the main SDRAM.
Caution:
There are two sub-ranges within the PCI memory address range defined as APIC configuration
space and High BIOS address range. As an Internal Graphics Device, the memory-mapped range
of the Internal Graphics Device
Must Not
overlap with these two ranges. Similarly, as an AGP
device, the AGP memory window and graphics aperture window
Must Not
overlap with these two
ranges. These ranges are described in detail in the following paragraphs.
APIC Configuration Space (FEC0_0000h–FECF_FFFFh, FEE0_0000h–
FEEF_FFFFh)
This range is reserved for APIC configuration space that includes the default I/O APIC
configuration space. The default Local APIC configuration space is FEE0_0000h to FEEF_0FFFh.
Processor accesses to the Local APIC configuration space do not result in external bus activity
since the Local APIC configuration space is internal to the processor. However, an MTRR must be
programmed to make the Local APIC range uncacheable (UC). The Local APIC base address in
each processor should be relocated to the FEC0_0000h (4 GB–20 MB) to FECF_FFFFh range so
that one MTRR can be programmed to 64 KB for the Local and I/O APICs. The I/O APIC(s)
usually reside in the ICH5 portion of the chipset or as a stand-alone component.
I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/O APIC is
located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h where
x
is the I/O APIC
unit number 0 through F(hex). This address range will be normally mapped to the hub interface.
Note:
There is no provision to support an I/O APIC device on AGP.
The address range between the APIC configuration space and the High BIOS (FED0_0000h to
FFDF_FFFFh) is always mapped to the hub interface.
High BIOS Area (FFE0_0000h–FFFF_FFFFh)
The top 2 MB of the Extended Memory Region is reserved for System BIOS (High BIOS),
extended BIOS for PCI devices, and the A20 alias of the system BIOS. The processor begins
execution from the High BIOS after reset. This region is mapped to the hub interface so that the
upper subset of this region aliases to 16-MB–256-KB range
.
The actual address space required for
the BIOS is less than 2 MB but the minimum processor MTRR range for this region is 2 MB so that
the full 2 MB must be considered.