Intel
82865G/82865GV GMCH Datasheet
41
Signal Description
2.7
Clocks, Reset, and Miscellaneous Signals
Signal Name
Type
Description
HCLKP
HCLKN
I
CMOS
Differential Host Clock In:
These pins receive a low voltage differential host
clock from the external clock synthesizer. This clock is used by all of the GMCH
logic that is in the Host clock domain 0.7 V.
GCLKIN
I
LVTTL
66 MHz Clock In:
. This pin receives a 66 MHz clock from the clock synthesizer.
This clock is used by AGP/PCI and HI clock domains.
NOTE:
This clock input is required to be 3.3 V tolerant.
DREFCLK
I
LVTTL
Display Clock Input:
This pin provides a 48 MHz input clock to the Display PLL
that is used for 2D/Video/Flat Panel and DAC.
NOTE:
This clock input is required to be 3.3 V tolerant.
RSTIN#
I
LVTTL
Reset In:
When asserted this signal will asynchronously reset the GMCH logic.
This signal is connected to the PCIRST# output of the ICH5. All AGP/PCI output
and bi-directional signals will also tri-state compliant to PCI Rev 2.0 and 2.1
specifications. This input should have a Schmitt trigger to avoid spurious resets.
NOTE:
This input needs to be 3.3 V tolerant.
PWROK
I
LVTTL
Power OK:
When asserted, PWROK is an indication to the GMCH that the core
power and GCLKIN have been stable for at least 10 μs.
EXTTS#
I
LVTTL
External Thermal Sensor Input
: Open-Drain signal indicating an Over-Temp
condition in the platform. This signal should remains asserted for as long as the
Over-temp Condition exists. This input pin can be programmed to activate
hardware management of memory reads and writes and/or trigger software
interrupts.
TESTIN#
I
Test Input. This signal is used in the GMCH XOR test mode. See
Chapter 8
for
use.