192
Intel
82865G/82865GV GMCH Datasheet
Electrical Characteristics
1.5 V CSA Interface
8
V
IL_CI
(e)
CSA Interface Input Low
Voltage
–
0.3
CI_VREF – 0.1
V
V
IH_CI
(e)
CSA Interface Input High
Voltage
CI_VREF + 0.1
1.2
V
V
OL_CI
(e)
CSA Interface Output
Low Voltage
0.05
V
I
OL
= 1 mA
V
OH_CI
(e)
CSA Interface Output
High Voltage
0.6
1.2
V
I
OUT
= 0.8/R
TT
,
R
TT
= 60
I
LEAK_CI
(e)
CSA Interface Input
Leakage Current
±
50
μ
A
C
IN_CI
(e)
CSA Interface Input
Capacitance
5
pF
F
C
=1 MHz
VTT DC Characteristics
V
IL_AGTL+
(g,h)
Host AGTL+ Input Low
Voltage
HDVREF
–
(0.04*Vsh)
V
V
IH_AGTL+
(g,h)
Host AGTL+ Input High
Voltage
HDVREF + (0.04*Vsh)
V
V
OL_AGTL+
(g,i)
Host AGTL+ Output Low
Voltage
1/4* Vsh
V
V
OH_AGTL+
(g,i)
Host AGTL+ Output High
Voltage
(Vsh-0.1) * 0.95
Vsh
V
I
OL_AGTL+
(g,i)
Host AGTL+ Output Low
Current
0.75 * Vshmax / Rttmin
mA
Rtt
min
=57
I
LEAK_AGTL+
(g,h)
Host AGTL+ Input
Leakage Current
±
25
μ
A
V
OL
<Vpad<VTT
C
PAD_AGTL+
(g,h)
Host AGTL+ Input
Capacitance
1
3.3
pF
F
C
=1 MHz
2.6 V DDR System Memory
V
IL_DDR(DC)
(l)
DDR Input Low Voltage
–
0.1 * VCC_DDR
SMVREF
–
0.15
V
V
IH_DDR(DC)
(l)
DDR Input High Voltage
SMVREF + 0.15
VCC_DDR
V
V
IL_DDR(AC)
(l)
DDR Input Low Voltage
–
0.1 * VCC_DDR
SMVREF
–
0.31
V
V
IH_DDR(AC)
(l)
DDR Input High Voltage
SMVREF + 0.31
VCC_DDR
V
V
OL_DDR
(l,m,v)
DDR Output Low Voltage
0.600
V
With 50
termination to
DDR VTT.
V
OH_DDR
(l,m,v)
DDR Output High
Voltage
VCC_DDR – 0.600
V
With 50
termination to
DDR VTT.
I
OL_DDR
(l,m)
DDR Output Low Current
25
mA
With 50
termination to
DDR VTT.
I
OH_DDR
(l,m)
DDR Output High
Current
–
25
mA
With 50
termination to
DDR VTT.
I
OL_DDR RCOMP
(v)
DDR RCOMP Output
Low Current
50
mA
I
OH_DDR RCOMP
(v)
DDR RCOMP Output
High Current
–
50
mA
I
Leak_DDR
(l)
Input Leakage Current
±
15
μ
A
C
IN_DDR
(l)
DDR Input /Output Pin
Capacitance
5.5
pF
F
C
=1 MHz
Table 38. DC Characteristics (Sheet 2 of 3)
Symbol
Signal
Group
Parameter
Min
Nom
Max
Unit
Notes