Intel
82865G/82865GV GMCH Datasheet
95
Register Description
3.6.16
SSTS1—Secondary Status Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
1E–1Fh
02A0h
RO, R/WC
16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with
secondary side (i.e., PCI_B/AGP side) of the virtual PCI-to-PCI bridge in the GMCH.
Bit
Descriptions
15
Detected Parity Error (DPE)—R/WC.
0 = No parity error detected.
1 = GMCH detected a parity error in the address or data phase of PCI_B/AGP bus transactions.
NOTE:
Software clears this bit by writing a 1 to it.
14
Received System Error (RSE)—RO.
Hardwired to 0. GMCH does not have a SERR# signal pin
on the AGP interface.
13
Received Master Abort Status (RMAS)—R/WC.
0 = No master abort termination.
1 = GMCH terminated a Host-to-PCI_B/AGP with an unexpected master abort.
NOTE:
Software clears this bit by writing a 1 to it.
12
Received Target Abort Status (RTAS)—R/WC.
0 = No target abort termination.
1 = GMCH-initiated transaction on PCI_B/AGP is terminated with a target abort.
NOTE:
Software clears this bit by writing a 1 to it.
11
Signaled Target Abort Status (STAS)—RO.
Hardwired to 0. GMCH does not generate target
abort on PCI_B/AGP.
10:9
DEVSEL# Timing (DEVT)—RO.
This 2-bit field indicates the timing of the DEVSEL# signal when
the GMCH responds as a target on PCI_B/AGP. This field is hardwired to 01b (medium) to indicate
the time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle.
8
Master Data Parity Error Detected (DPD)—RO.
Hardwired to 0. GMCH does not implement
G_PERR# signal on PCI_B.
7
Fast Back-to-Back (FB2B)—RO.
Hardwired to 1. GMCH as a target supports fast back-to-back
transactions on PCI_B/AGP.
6
Reserved.
5
66/60 MHz capability (CAP66)—RO.
Hardwired to 1 to indicate that the AGP/PCI_B bus is
capable of 66 MHz operation.
4:0
Reserved.