116
Intel
82865G/82865GV GMCH Datasheet
Register Description
3.8.4
PCISTS3—PCI Status Register (Device 3)
Address Offset:
Default Value:
Access:
Size:
06h
07h
00A0h
RO, R/WC
16 bits
PCISTS3 is a 16-bit status register that reports the occurrence of error conditions associated with
primary side of the virtual PCI-to-CSA bridge in the GMCH.
Note:
For R/WC bits, software must write a 1 to clear bits that are set.
Bit
Description
15
Detected Parity Error (DPE)
RO
. Hardwired to 0. Parity is not supported on the primary side of
this device.
14
Signaled System Error (SSE)
R/WC
.
0 = No SERR message generated by GMCH Device 3 over HI.
1 = GMCH Device 3 generated a SERR message over HI for any enabled Device 3 error condition.
Device 3 error conditions are enabled in the ERRCMD, PCICMD3, and BCTRL3 registers.
Device 3 error flags are read/reset from the ERRSTS and SSTS3 register.
13
Received Master Abort Status (RMAS)
RO
. Hardwired to 0. The concept of a master abort does
not exist on the primary side of this device.
12
Received Target Abort Status (RTAS)
RO
. Hardwired to 0. The concept of a target abort does
not exist on the primary side of this device.
11
Signaled Target Abort Status (STAS)—RO.
Hardwired to 0. The concept of a target abort does not
exist on primary side of this device.
10:9
DEVSEL# Timing (DEVT)—RO.
The Hardwired to 00b. GMCH does not support subtractive
decoding devices on bus 0. The value 00b indicates that Device 3 uses the fastest possible decode.
8
Data Parity Detected (DPD)
RO
. Hardwired to 0. Parity Error Response is hardwired to disabled
(and the GMCH does not support any parity detection on the primary side of this device).
7
Fast Back-to-Back (FB2B)—RO.
Hardwired to 1. The interface always supports fast back-to-back
writes.
6
Reserved.
5
66/60 MHz PCI Capable (CAP66)—RO.
Hardwired to 1. CSA is 66 MHz capable.
4:0
Reserved.